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authorPaulo Alcantara <pcacjr@zytor.com>2015-07-08 00:53:55 -0300
committerPaulo Alcantara <pcacjr@zytor.com>2015-07-08 00:53:55 -0300
commit6cb7efc8b44739111ab02878d762aac045ea30c4 (patch)
tree82e74cfc97057f5a357f078df21873d3dee42ec4
parente8b21f32f958dce5b6b23b7e52e731972619c834 (diff)
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qemu-tco-test-fix.zip
tco-test: fix access of LPC device registerstco-test-fix
As per ICH9 spec, the LPC I interface registers are accessed through PCI configuration space D31:F0, so mapping LPC device with qpci_iomap() and then calling qpci_config_(read|write)() to access its registers did not make any sense. Reported-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Paulo Alcantara <pcacjr@zytor.com>
-rw-r--r--tests/tco-test.c17
1 files changed, 3 insertions, 14 deletions
diff --git a/tests/tco-test.c b/tests/tco-test.c
index 6a48188b9..ff25d29f1 100644
--- a/tests/tco-test.c
+++ b/tests/tco-test.c
@@ -44,7 +44,6 @@ typedef struct {
const char *args;
bool noreboot;
QPCIDevice *dev;
- void *lpc_base;
void *tco_io_base;
} TestData;
@@ -65,22 +64,12 @@ static void test_init(TestData *d)
d->dev = qpci_device_find(bus, QPCI_DEVFN(0x1f, 0x00));
g_assert(d->dev != NULL);
- /* map PCI-to-LPC bridge interface BAR */
- d->lpc_base = qpci_iomap(d->dev, 0, NULL);
-
- qpci_device_enable(d->dev);
-
- g_assert(d->lpc_base != NULL);
-
/* set ACPI PM I/O space base address */
- qpci_config_writel(d->dev, (uintptr_t)d->lpc_base + ICH9_LPC_PMBASE,
- PM_IO_BASE_ADDR | 0x1);
+ qpci_config_writel(d->dev, ICH9_LPC_PMBASE, PM_IO_BASE_ADDR | 0x1);
/* enable ACPI I/O */
- qpci_config_writeb(d->dev, (uintptr_t)d->lpc_base + ICH9_LPC_ACPI_CTRL,
- 0x80);
+ qpci_config_writeb(d->dev, ICH9_LPC_ACPI_CTRL, 0x80);
/* set Root Complex BAR */
- qpci_config_writel(d->dev, (uintptr_t)d->lpc_base + ICH9_LPC_RCBA,
- RCBA_BASE_ADDR | 0x1);
+ qpci_config_writel(d->dev, ICH9_LPC_RCBA, RCBA_BASE_ADDR | 0x1);
d->tco_io_base = (void *)((uintptr_t)PM_IO_BASE_ADDR + 0x60);
}