summaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorMichel Dänzer <michel.daenzer@amd.com>2012-08-16 10:37:44 +0200
committerMichel Dänzer <michel@daenzer.net>2012-08-16 12:01:16 +0200
commit1b11395a36a44a902cfb3e1783758544662df73f (patch)
tree403ab4d737404a91d88097dd64b88ce99891f5e7
parent51d9f37a72b3c7893204efbbeca034d1581d30f1 (diff)
downloadmesa-1b11395a36a44a902cfb3e1783758544662df73f.tar.gz
mesa-1b11395a36a44a902cfb3e1783758544662df73f.tar.xz
mesa-1b11395a36a44a902cfb3e1783758544662df73f.zip
radeonsi: Fix symbol conflicts with r600g.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=50389 Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
-rw-r--r--src/gallium/drivers/radeonsi/r600.h10
-rw-r--r--src/gallium/drivers/radeonsi/r600_blit.c10
-rw-r--r--src/gallium/drivers/radeonsi/r600_buffer.c8
-rw-r--r--src/gallium/drivers/radeonsi/r600_hw_context.c18
-rw-r--r--src/gallium/drivers/radeonsi/r600_resource.c6
-rw-r--r--src/gallium/drivers/radeonsi/r600_resource.h20
-rw-r--r--src/gallium/drivers/radeonsi/r600_texture.c414
-rw-r--r--src/gallium/drivers/radeonsi/radeonsi_pipe.c10
-rw-r--r--src/gallium/drivers/radeonsi/radeonsi_pipe.h22
-rw-r--r--src/gallium/drivers/radeonsi/si_state_draw.c4
10 files changed, 254 insertions, 268 deletions
diff --git a/src/gallium/drivers/radeonsi/r600.h b/src/gallium/drivers/radeonsi/r600.h
index df9e7a08fa..c2c22c4d84 100644
--- a/src/gallium/drivers/radeonsi/r600.h
+++ b/src/gallium/drivers/radeonsi/r600.h
@@ -98,8 +98,8 @@ struct r600_so_target {
struct r600_context;
struct r600_screen;
-void r600_get_backend_mask(struct r600_context *ctx);
-void r600_context_flush(struct r600_context *ctx, unsigned flags);
+void si_get_backend_mask(struct r600_context *ctx);
+void si_context_flush(struct r600_context *ctx, unsigned flags);
struct r600_query *r600_context_query_create(struct r600_context *ctx, unsigned query_type);
void r600_context_query_destroy(struct r600_context *ctx, struct r600_query *query);
@@ -112,11 +112,11 @@ void r600_context_queries_suspend(struct r600_context *ctx);
void r600_context_queries_resume(struct r600_context *ctx);
void r600_query_predication(struct r600_context *ctx, struct r600_query *query, int operation,
int flag_wait);
-void r600_context_emit_fence(struct r600_context *ctx, struct si_resource *fence,
- unsigned offset, unsigned value);
+void si_context_emit_fence(struct r600_context *ctx, struct si_resource *fence,
+ unsigned offset, unsigned value);
void r600_context_draw_opaque_count(struct r600_context *ctx, struct r600_so_target *t);
-void r600_need_cs_space(struct r600_context *ctx, unsigned num_dw, boolean count_draw_in);
+void si_need_cs_space(struct r600_context *ctx, unsigned num_dw, boolean count_draw_in);
int si_context_init(struct r600_context *ctx);
diff --git a/src/gallium/drivers/radeonsi/r600_blit.c b/src/gallium/drivers/radeonsi/r600_blit.c
index 9a0cd806bc..4406204b51 100644
--- a/src/gallium/drivers/radeonsi/r600_blit.c
+++ b/src/gallium/drivers/radeonsi/r600_blit.c
@@ -113,7 +113,7 @@ static unsigned u_num_layers(struct pipe_resource *r, unsigned level)
}
}
-void r600_blit_uncompress_depth(struct pipe_context *ctx, struct r600_resource_texture *texture)
+void si_blit_uncompress_depth(struct pipe_context *ctx, struct r600_resource_texture *texture)
{
struct r600_context *rctx = (struct r600_context *)ctx;
unsigned layer, level;
@@ -153,7 +153,7 @@ void r600_blit_uncompress_depth(struct pipe_context *ctx, struct r600_resource_t
texture->dirty_db = FALSE;
}
-void r600_flush_depth_textures(struct r600_context *rctx)
+void si_flush_depth_textures(struct r600_context *rctx)
{
unsigned int i;
@@ -173,7 +173,7 @@ void r600_flush_depth_textures(struct r600_context *rctx)
if (tex->is_flushing_texture)
continue;
- r600_blit_uncompress_depth(&rctx->context, tex);
+ si_blit_uncompress_depth(&rctx->context, tex);
}
/* also check CB here */
@@ -187,7 +187,7 @@ void r600_flush_depth_textures(struct r600_context *rctx)
if (tex->is_flushing_texture)
continue;
- r600_blit_uncompress_depth(&rctx->context, tex);
+ si_blit_uncompress_depth(&rctx->context, tex);
}
}
@@ -374,7 +374,7 @@ static void r600_resource_copy_region(struct pipe_context *ctx,
r600_reset_blittable_to_compressed(dst, dst_level, &orig_info[1]);
}
-void r600_init_blit_functions(struct r600_context *rctx)
+void si_init_blit_functions(struct r600_context *rctx)
{
rctx->context.clear = r600_clear;
rctx->context.clear_render_target = r600_clear_render_target;
diff --git a/src/gallium/drivers/radeonsi/r600_buffer.c b/src/gallium/drivers/radeonsi/r600_buffer.c
index 76de9410e4..ec9d87e486 100644
--- a/src/gallium/drivers/radeonsi/r600_buffer.c
+++ b/src/gallium/drivers/radeonsi/r600_buffer.c
@@ -114,7 +114,7 @@ static const struct u_resource_vtbl r600_buffer_vtbl =
NULL /* transfer_inline_write */
};
-bool r600_init_resource(struct r600_screen *rscreen,
+bool si_init_resource(struct r600_screen *rscreen,
struct si_resource *res,
unsigned size, unsigned alignment,
unsigned bind, unsigned usage)
@@ -156,8 +156,8 @@ bool r600_init_resource(struct r600_screen *rscreen,
return true;
}
-struct pipe_resource *r600_buffer_create(struct pipe_screen *screen,
- const struct pipe_resource *templ)
+struct pipe_resource *si_buffer_create(struct pipe_screen *screen,
+ const struct pipe_resource *templ)
{
struct r600_screen *rscreen = (struct r600_screen*)screen;
struct si_resource *rbuffer;
@@ -171,7 +171,7 @@ struct pipe_resource *r600_buffer_create(struct pipe_screen *screen,
rbuffer->b.b.screen = screen;
rbuffer->b.vtbl = &r600_buffer_vtbl;
- if (!r600_init_resource(rscreen, rbuffer, templ->width0, alignment, templ->bind, templ->usage)) {
+ if (!si_init_resource(rscreen, rbuffer, templ->width0, alignment, templ->bind, templ->usage)) {
FREE(rbuffer);
return NULL;
}
diff --git a/src/gallium/drivers/radeonsi/r600_hw_context.c b/src/gallium/drivers/radeonsi/r600_hw_context.c
index f8b1b38702..685f195173 100644
--- a/src/gallium/drivers/radeonsi/r600_hw_context.c
+++ b/src/gallium/drivers/radeonsi/r600_hw_context.c
@@ -33,7 +33,7 @@
#define GROUP_FORCE_NEW_BLOCK 0
/* Get backends mask */
-void r600_get_backend_mask(struct r600_context *ctx)
+void si_get_backend_mask(struct r600_context *ctx)
{
struct radeon_winsys_cs *cs = ctx->cs;
struct si_resource *buffer;
@@ -116,7 +116,7 @@ err:
}
/* initialize */
-void r600_need_cs_space(struct r600_context *ctx, unsigned num_dw,
+void si_need_cs_space(struct r600_context *ctx, unsigned num_dw,
boolean count_draw_in)
{
/* The number of dwords we already used in the CS so far. */
@@ -177,7 +177,7 @@ static void r600_flush_framebuffer(struct r600_context *ctx)
ctx->flags &= ~R600_CONTEXT_DST_CACHES_DIRTY;
}
-void r600_context_flush(struct r600_context *ctx, unsigned flags)
+void si_context_flush(struct r600_context *ctx, unsigned flags)
{
struct radeon_winsys_cs *cs = ctx->cs;
bool queries_suspended = false;
@@ -235,12 +235,12 @@ void r600_context_flush(struct r600_context *ctx, unsigned flags)
si_pm4_reset_emitted(ctx);
}
-void r600_context_emit_fence(struct r600_context *ctx, struct si_resource *fence_bo, unsigned offset, unsigned value)
+void si_context_emit_fence(struct r600_context *ctx, struct si_resource *fence_bo, unsigned offset, unsigned value)
{
struct radeon_winsys_cs *cs = ctx->cs;
uint64_t va;
- r600_need_cs_space(ctx, 10, FALSE);
+ si_need_cs_space(ctx, 10, FALSE);
va = r600_resource_va(&ctx->screen->screen, (void*)fence_bo);
va = va + (offset << 2);
@@ -364,7 +364,7 @@ void r600_query_begin(struct r600_context *ctx, struct r600_query *query)
uint32_t *results;
uint64_t va;
- r600_need_cs_space(ctx, query->num_cs_dw * 2, TRUE);
+ si_need_cs_space(ctx, query->num_cs_dw * 2, TRUE);
new_results_end = (query->results_end + query->result_size) % query->buffer->b.b.width0;
@@ -495,7 +495,7 @@ void r600_query_predication(struct r600_context *ctx, struct r600_query *query,
uint64_t va;
if (operation == PREDICATION_OP_CLEAR) {
- r600_need_cs_space(ctx, 3, FALSE);
+ si_need_cs_space(ctx, 3, FALSE);
cs->buf[cs->cdw++] = PKT3(PKT3_SET_PREDICATION, 1, 0);
cs->buf[cs->cdw++] = 0;
@@ -509,7 +509,7 @@ void r600_query_predication(struct r600_context *ctx, struct r600_query *query,
count = (query->buffer->b.b.width0 + query->results_end - query->results_start) % query->buffer->b.b.width0;
count /= query->result_size;
- r600_need_cs_space(ctx, 5 * count, TRUE);
+ si_need_cs_space(ctx, 5 * count, TRUE);
op = PRED_OP(operation) | PREDICATION_DRAW_VISIBLE |
(flag_wait ? PREDICATION_HINT_WAIT : PREDICATION_HINT_NOWAIT_DRAW);
@@ -647,7 +647,7 @@ void r600_context_queries_resume(struct r600_context *ctx)
void r600_context_draw_opaque_count(struct r600_context *ctx, struct r600_so_target *t)
{
struct radeon_winsys_cs *cs = ctx->cs;
- r600_need_cs_space(ctx, 14 + 21, TRUE);
+ si_need_cs_space(ctx, 14 + 21, TRUE);
cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONTEXT_REG, 1, 0);
cs->buf[cs->cdw++] = (R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET - SI_CONTEXT_REG_OFFSET) >> 2;
diff --git a/src/gallium/drivers/radeonsi/r600_resource.c b/src/gallium/drivers/radeonsi/r600_resource.c
index d9be706b6b..a4888a703b 100644
--- a/src/gallium/drivers/radeonsi/r600_resource.c
+++ b/src/gallium/drivers/radeonsi/r600_resource.c
@@ -27,9 +27,9 @@ static struct pipe_resource *r600_resource_create(struct pipe_screen *screen,
const struct pipe_resource *templ)
{
if (templ->target == PIPE_BUFFER) {
- return r600_buffer_create(screen, templ);
+ return si_buffer_create(screen, templ);
} else {
- return r600_texture_create(screen, templ);
+ return si_texture_create(screen, templ);
}
}
@@ -40,7 +40,7 @@ static struct pipe_resource *r600_resource_from_handle(struct pipe_screen * scre
if (templ->target == PIPE_BUFFER) {
return NULL;
} else {
- return r600_texture_from_handle(screen, templ, whandle);
+ return si_texture_from_handle(screen, templ, whandle);
}
}
diff --git a/src/gallium/drivers/radeonsi/r600_resource.h b/src/gallium/drivers/radeonsi/r600_resource.h
index 678bf12778..e539eedc3b 100644
--- a/src/gallium/drivers/radeonsi/r600_resource.h
+++ b/src/gallium/drivers/radeonsi/r600_resource.h
@@ -70,26 +70,14 @@ struct r600_surface {
void r600_init_screen_resource_functions(struct pipe_screen *screen);
/* r600_texture */
-struct pipe_resource *r600_texture_create(struct pipe_screen *screen,
+struct pipe_resource *si_texture_create(struct pipe_screen *screen,
const struct pipe_resource *templ);
-struct pipe_resource *r600_texture_from_handle(struct pipe_screen *screen,
- const struct pipe_resource *base,
- struct winsys_handle *whandle);
+struct pipe_resource *si_texture_from_handle(struct pipe_screen *screen,
+ const struct pipe_resource *base,
+ struct winsys_handle *whandle);
int r600_texture_depth_flush(struct pipe_context *ctx, struct pipe_resource *texture, boolean just_create);
-/* r600_texture.c texture transfer functions. */
-struct pipe_transfer* r600_texture_get_transfer(struct pipe_context *ctx,
- struct pipe_resource *texture,
- unsigned level,
- unsigned usage,
- const struct pipe_box *box);
-void r600_texture_transfer_destroy(struct pipe_context *ctx,
- struct pipe_transfer *trans);
-void* r600_texture_transfer_map(struct pipe_context *ctx,
- struct pipe_transfer* transfer);
-void r600_texture_transfer_unmap(struct pipe_context *ctx,
- struct pipe_transfer* transfer);
struct r600_context;
diff --git a/src/gallium/drivers/radeonsi/r600_texture.c b/src/gallium/drivers/radeonsi/r600_texture.c
index 392f177f63..905f218422 100644
--- a/src/gallium/drivers/radeonsi/r600_texture.c
+++ b/src/gallium/drivers/radeonsi/r600_texture.c
@@ -66,7 +66,7 @@ static void r600_copy_from_staging_texture(struct pipe_context *ctx, struct r600
0, &sbox);
}
-unsigned r600_texture_get_offset(struct r600_resource_texture *rtex,
+static unsigned r600_texture_get_offset(struct r600_resource_texture *rtex,
unsigned level, unsigned layer)
{
unsigned offset = rtex->offset[level];
@@ -489,15 +489,209 @@ static void r600_texture_destroy(struct pipe_screen *screen,
FREE(rtex);
}
+/* Needs adjustment for pixelformat:
+ */
+static INLINE unsigned u_box_volume( const struct pipe_box *box )
+{
+ return box->width * box->depth * box->height;
+};
+
+static struct pipe_transfer* si_texture_get_transfer(struct pipe_context *ctx,
+ struct pipe_resource *texture,
+ unsigned level,
+ unsigned usage,
+ const struct pipe_box *box)
+{
+ struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture;
+ struct pipe_resource resource;
+ struct r600_transfer *trans;
+ int r;
+ boolean use_staging_texture = FALSE;
+
+ /* We cannot map a tiled texture directly because the data is
+ * in a different order, therefore we do detiling using a blit.
+ *
+ * Also, use a temporary in GTT memory for read transfers, as
+ * the CPU is much happier reading out of cached system memory
+ * than uncached VRAM.
+ */
+ if (R600_TEX_IS_TILED(rtex, level))
+ use_staging_texture = TRUE;
+
+ if ((usage & PIPE_TRANSFER_READ) && u_box_volume(box) > 1024)
+ use_staging_texture = TRUE;
+
+ /* XXX: Use a staging texture for uploads if the underlying BO
+ * is busy. No interface for checking that currently? so do
+ * it eagerly whenever the transfer doesn't require a readback
+ * and might block.
+ */
+ if ((usage & PIPE_TRANSFER_WRITE) &&
+ !(usage & (PIPE_TRANSFER_READ |
+ PIPE_TRANSFER_DONTBLOCK |
+ PIPE_TRANSFER_UNSYNCHRONIZED)))
+ use_staging_texture = TRUE;
+
+ if (!permit_hardware_blit(ctx->screen, texture) ||
+ (texture->flags & R600_RESOURCE_FLAG_TRANSFER))
+ use_staging_texture = FALSE;
+
+ if (use_staging_texture && (usage & PIPE_TRANSFER_MAP_DIRECTLY))
+ return NULL;
+
+ trans = CALLOC_STRUCT(r600_transfer);
+ if (trans == NULL)
+ return NULL;
+ pipe_resource_reference(&trans->transfer.resource, texture);
+ trans->transfer.level = level;
+ trans->transfer.usage = usage;
+ trans->transfer.box = *box;
+ if (rtex->depth) {
+ /* XXX: only readback the rectangle which is being mapped?
+ */
+ /* XXX: when discard is true, no need to read back from depth texture
+ */
+ r = r600_texture_depth_flush(ctx, texture, FALSE);
+ if (r < 0) {
+ R600_ERR("failed to create temporary texture to hold untiled copy\n");
+ pipe_resource_reference(&trans->transfer.resource, NULL);
+ FREE(trans);
+ return NULL;
+ }
+ trans->transfer.stride = rtex->flushed_depth_texture->pitch_in_bytes[level];
+ trans->offset = r600_texture_get_offset(rtex->flushed_depth_texture, level, box->z);
+ return &trans->transfer;
+ } else if (use_staging_texture) {
+ resource.target = PIPE_TEXTURE_2D;
+ resource.format = texture->format;
+ resource.width0 = box->width;
+ resource.height0 = box->height;
+ resource.depth0 = 1;
+ resource.array_size = 1;
+ resource.last_level = 0;
+ resource.nr_samples = 0;
+ resource.usage = PIPE_USAGE_STAGING;
+ resource.bind = 0;
+ resource.flags = R600_RESOURCE_FLAG_TRANSFER;
+ /* For texture reading, the temporary (detiled) texture is used as
+ * a render target when blitting from a tiled texture. */
+ if (usage & PIPE_TRANSFER_READ) {
+ resource.bind |= PIPE_BIND_RENDER_TARGET;
+ }
+ /* For texture writing, the temporary texture is used as a sampler
+ * when blitting into a tiled texture. */
+ if (usage & PIPE_TRANSFER_WRITE) {
+ resource.bind |= PIPE_BIND_SAMPLER_VIEW;
+ }
+ /* Create the temporary texture. */
+ trans->staging_texture = ctx->screen->resource_create(ctx->screen, &resource);
+ if (trans->staging_texture == NULL) {
+ R600_ERR("failed to create temporary texture to hold untiled copy\n");
+ pipe_resource_reference(&trans->transfer.resource, NULL);
+ FREE(trans);
+ return NULL;
+ }
+
+ trans->transfer.stride =
+ ((struct r600_resource_texture *)trans->staging_texture)->pitch_in_bytes[0];
+ if (usage & PIPE_TRANSFER_READ) {
+ r600_copy_to_staging_texture(ctx, trans);
+ /* Always referenced in the blit. */
+ radeonsi_flush(ctx, NULL, 0);
+ }
+ return &trans->transfer;
+ }
+ trans->transfer.stride = rtex->pitch_in_bytes[level];
+ trans->transfer.layer_stride = rtex->layer_size[level];
+ trans->offset = r600_texture_get_offset(rtex, level, box->z);
+ return &trans->transfer;
+}
+
+static void si_texture_transfer_destroy(struct pipe_context *ctx,
+ struct pipe_transfer *transfer)
+{
+ struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
+ struct pipe_resource *texture = transfer->resource;
+ struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture;
+
+ if (rtransfer->staging_texture) {
+ if (transfer->usage & PIPE_TRANSFER_WRITE) {
+ r600_copy_from_staging_texture(ctx, rtransfer);
+ }
+ pipe_resource_reference(&rtransfer->staging_texture, NULL);
+ }
+
+ if (rtex->depth && !rtex->is_flushing_texture) {
+ if ((transfer->usage & PIPE_TRANSFER_WRITE) && rtex->flushed_depth_texture)
+ r600_blit_push_depth(ctx, rtex);
+ }
+
+ pipe_resource_reference(&transfer->resource, NULL);
+ FREE(transfer);
+}
+
+static void* si_texture_transfer_map(struct pipe_context *ctx,
+ struct pipe_transfer* transfer)
+{
+ struct r600_context *rctx = (struct r600_context *)ctx;
+ struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
+ struct radeon_winsys_cs_handle *buf;
+ enum pipe_format format = transfer->resource->format;
+ unsigned offset = 0;
+ char *map;
+
+ if (rtransfer->staging_texture) {
+ buf = si_resource(rtransfer->staging_texture)->cs_buf;
+ } else {
+ struct r600_resource_texture *rtex = (struct r600_resource_texture*)transfer->resource;
+
+ if (rtex->flushed_depth_texture)
+ buf = si_resource(rtex->flushed_depth_texture)->cs_buf;
+ else
+ buf = si_resource(transfer->resource)->cs_buf;
+
+ offset = rtransfer->offset +
+ transfer->box.y / util_format_get_blockheight(format) * transfer->stride +
+ transfer->box.x / util_format_get_blockwidth(format) * util_format_get_blocksize(format);
+ }
+
+ if (!(map = rctx->ws->buffer_map(buf, rctx->cs, transfer->usage))) {
+ return NULL;
+ }
+
+ return map + offset;
+}
+
+static void si_texture_transfer_unmap(struct pipe_context *ctx,
+ struct pipe_transfer* transfer)
+{
+ struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
+ struct r600_context *rctx = (struct r600_context*)ctx;
+ struct radeon_winsys_cs_handle *buf;
+
+ if (rtransfer->staging_texture) {
+ buf = si_resource(rtransfer->staging_texture)->cs_buf;
+ } else {
+ struct r600_resource_texture *rtex = (struct r600_resource_texture*)transfer->resource;
+
+ if (rtex->flushed_depth_texture) {
+ buf = si_resource(rtex->flushed_depth_texture)->cs_buf;
+ } else {
+ buf = si_resource(transfer->resource)->cs_buf;
+ }
+ }
+ rctx->ws->buffer_unmap(buf);
+}
+
static const struct u_resource_vtbl r600_texture_vtbl =
{
r600_texture_get_handle, /* get_handle */
r600_texture_destroy, /* resource_destroy */
- r600_texture_get_transfer, /* get_transfer */
- r600_texture_transfer_destroy, /* transfer_destroy */
- r600_texture_transfer_map, /* transfer_map */
+ si_texture_get_transfer, /* get_transfer */
+ si_texture_transfer_destroy, /* transfer_destroy */
+ si_texture_transfer_map, /* transfer_map */
u_default_transfer_flush_region,/* transfer_flush_region */
- r600_texture_transfer_unmap, /* transfer_unmap */
+ si_texture_transfer_unmap, /* transfer_unmap */
NULL /* transfer_inline_write */
};
@@ -546,7 +740,7 @@ r600_texture_create_object(struct pipe_screen *screen,
unsigned base_align = r600_get_base_alignment(screen, ptex->format, array_mode);
base_align = rtex->surface.bo_alignment;
- if (!r600_init_resource(rscreen, resource, rtex->size, base_align, base->bind, base->usage)) {
+ if (!si_init_resource(rscreen, resource, rtex->size, base_align, base->bind, base->usage)) {
FREE(rtex);
return NULL;
}
@@ -559,8 +753,8 @@ r600_texture_create_object(struct pipe_screen *screen,
return rtex;
}
-struct pipe_resource *r600_texture_create(struct pipe_screen *screen,
- const struct pipe_resource *templ)
+struct pipe_resource *si_texture_create(struct pipe_screen *screen,
+ const struct pipe_resource *templ)
{
struct r600_screen *rscreen = (struct r600_screen*)screen;
struct radeon_surface surface;
@@ -625,9 +819,9 @@ static void r600_surface_destroy(struct pipe_context *pipe,
FREE(surface);
}
-struct pipe_resource *r600_texture_from_handle(struct pipe_screen *screen,
- const struct pipe_resource *templ,
- struct winsys_handle *whandle)
+struct pipe_resource *si_texture_from_handle(struct pipe_screen *screen,
+ const struct pipe_resource *templ,
+ struct winsys_handle *whandle)
{
struct r600_screen *rscreen = (struct r600_screen*)screen;
struct pb_buffer *buf = NULL;
@@ -701,205 +895,11 @@ out:
/* XXX: only do this if the depth texture has actually changed:
*/
- r600_blit_uncompress_depth(ctx, rtex);
+ si_blit_uncompress_depth(ctx, rtex);
return 0;
}
-/* Needs adjustment for pixelformat:
- */
-static INLINE unsigned u_box_volume( const struct pipe_box *box )
-{
- return box->width * box->depth * box->height;
-};
-
-struct pipe_transfer* r600_texture_get_transfer(struct pipe_context *ctx,
- struct pipe_resource *texture,
- unsigned level,
- unsigned usage,
- const struct pipe_box *box)
-{
- struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture;
- struct pipe_resource resource;
- struct r600_transfer *trans;
- int r;
- boolean use_staging_texture = FALSE;
-
- /* We cannot map a tiled texture directly because the data is
- * in a different order, therefore we do detiling using a blit.
- *
- * Also, use a temporary in GTT memory for read transfers, as
- * the CPU is much happier reading out of cached system memory
- * than uncached VRAM.
- */
- if (R600_TEX_IS_TILED(rtex, level))
- use_staging_texture = TRUE;
-
- if ((usage & PIPE_TRANSFER_READ) && u_box_volume(box) > 1024)
- use_staging_texture = TRUE;
-
- /* XXX: Use a staging texture for uploads if the underlying BO
- * is busy. No interface for checking that currently? so do
- * it eagerly whenever the transfer doesn't require a readback
- * and might block.
- */
- if ((usage & PIPE_TRANSFER_WRITE) &&
- !(usage & (PIPE_TRANSFER_READ |
- PIPE_TRANSFER_DONTBLOCK |
- PIPE_TRANSFER_UNSYNCHRONIZED)))
- use_staging_texture = TRUE;
-
- if (!permit_hardware_blit(ctx->screen, texture) ||
- (texture->flags & R600_RESOURCE_FLAG_TRANSFER))
- use_staging_texture = FALSE;
-
- if (use_staging_texture && (usage & PIPE_TRANSFER_MAP_DIRECTLY))
- return NULL;
-
- trans = CALLOC_STRUCT(r600_transfer);
- if (trans == NULL)
- return NULL;
- pipe_resource_reference(&trans->transfer.resource, texture);
- trans->transfer.level = level;
- trans->transfer.usage = usage;
- trans->transfer.box = *box;
- if (rtex->depth) {
- /* XXX: only readback the rectangle which is being mapped?
- */
- /* XXX: when discard is true, no need to read back from depth texture
- */
- r = r600_texture_depth_flush(ctx, texture, FALSE);
- if (r < 0) {
- R600_ERR("failed to create temporary texture to hold untiled copy\n");
- pipe_resource_reference(&trans->transfer.resource, NULL);
- FREE(trans);
- return NULL;
- }
- trans->transfer.stride = rtex->flushed_depth_texture->pitch_in_bytes[level];
- trans->offset = r600_texture_get_offset(rtex->flushed_depth_texture, level, box->z);
- return &trans->transfer;
- } else if (use_staging_texture) {
- resource.target = PIPE_TEXTURE_2D;
- resource.format = texture->format;
- resource.width0 = box->width;
- resource.height0 = box->height;
- resource.depth0 = 1;
- resource.array_size = 1;
- resource.last_level = 0;
- resource.nr_samples = 0;
- resource.usage = PIPE_USAGE_STAGING;
- resource.bind = 0;
- resource.flags = R600_RESOURCE_FLAG_TRANSFER;
- /* For texture reading, the temporary (detiled) texture is used as
- * a render target when blitting from a tiled texture. */
- if (usage & PIPE_TRANSFER_READ) {
- resource.bind |= PIPE_BIND_RENDER_TARGET;
- }
- /* For texture writing, the temporary texture is used as a sampler
- * when blitting into a tiled texture. */
- if (usage & PIPE_TRANSFER_WRITE) {
- resource.bind |= PIPE_BIND_SAMPLER_VIEW;
- }
- /* Create the temporary texture. */
- trans->staging_texture = ctx->screen->resource_create(ctx->screen, &resource);
- if (trans->staging_texture == NULL) {
- R600_ERR("failed to create temporary texture to hold untiled copy\n");
- pipe_resource_reference(&trans->transfer.resource, NULL);
- FREE(trans);
- return NULL;
- }
-
- trans->transfer.stride =
- ((struct r600_resource_texture *)trans->staging_texture)->pitch_in_bytes[0];
- if (usage & PIPE_TRANSFER_READ) {
- r600_copy_to_staging_texture(ctx, trans);
- /* Always referenced in the blit. */
- radeonsi_flush(ctx, NULL, 0);
- }
- return &trans->transfer;
- }
- trans->transfer.stride = rtex->pitch_in_bytes[level];
- trans->transfer.layer_stride = rtex->layer_size[level];
- trans->offset = r600_texture_get_offset(rtex, level, box->z);
- return &trans->transfer;
-}
-
-void r600_texture_transfer_destroy(struct pipe_context *ctx,
- struct pipe_transfer *transfer)
-{
- struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
- struct pipe_resource *texture = transfer->resource;
- struct r600_resource_texture *rtex = (struct r600_resource_texture*)texture;
-
- if (rtransfer->staging_texture) {
- if (transfer->usage & PIPE_TRANSFER_WRITE) {
- r600_copy_from_staging_texture(ctx, rtransfer);
- }
- pipe_resource_reference(&rtransfer->staging_texture, NULL);
- }
-
- if (rtex->depth && !rtex->is_flushing_texture) {
- if ((transfer->usage & PIPE_TRANSFER_WRITE) && rtex->flushed_depth_texture)
- r600_blit_push_depth(ctx, rtex);
- }
-
- pipe_resource_reference(&transfer->resource, NULL);
- FREE(transfer);
-}
-
-void* r600_texture_transfer_map(struct pipe_context *ctx,
- struct pipe_transfer* transfer)
-{
- struct r600_context *rctx = (struct r600_context *)ctx;
- struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
- struct radeon_winsys_cs_handle *buf;
- enum pipe_format format = transfer->resource->format;
- unsigned offset = 0;
- char *map;
-
- if (rtransfer->staging_texture) {
- buf = si_resource(rtransfer->staging_texture)->cs_buf;
- } else {
- struct r600_resource_texture *rtex = (struct r600_resource_texture*)transfer->resource;
-
- if (rtex->flushed_depth_texture)
- buf = si_resource(rtex->flushed_depth_texture)->cs_buf;
- else
- buf = si_resource(transfer->resource)->cs_buf;
-
- offset = rtransfer->offset +
- transfer->box.y / util_format_get_blockheight(format) * transfer->stride +
- transfer->box.x / util_format_get_blockwidth(format) * util_format_get_blocksize(format);
- }
-
- if (!(map = rctx->ws->buffer_map(buf, rctx->cs, transfer->usage))) {
- return NULL;
- }
-
- return map + offset;
-}
-
-void r600_texture_transfer_unmap(struct pipe_context *ctx,
- struct pipe_transfer* transfer)
-{
- struct r600_transfer *rtransfer = (struct r600_transfer*)transfer;
- struct r600_context *rctx = (struct r600_context*)ctx;
- struct radeon_winsys_cs_handle *buf;
-
- if (rtransfer->staging_texture) {
- buf = si_resource(rtransfer->staging_texture)->cs_buf;
- } else {
- struct r600_resource_texture *rtex = (struct r600_resource_texture*)transfer->resource;
-
- if (rtex->flushed_depth_texture) {
- buf = si_resource(rtex->flushed_depth_texture)->cs_buf;
- } else {
- buf = si_resource(transfer->resource)->cs_buf;
- }
- }
- rctx->ws->buffer_unmap(buf);
-}
-
-void r600_init_surface_functions(struct r600_context *r600)
+void si_init_surface_functions(struct r600_context *r600)
{
r600->context.create_surface = r600_create_surface;
r600->context.surface_destroy = r600_surface_destroy;
diff --git a/src/gallium/drivers/radeonsi/radeonsi_pipe.c b/src/gallium/drivers/radeonsi/radeonsi_pipe.c
index 79a3d801b5..abcdfbf303 100644
--- a/src/gallium/drivers/radeonsi/radeonsi_pipe.c
+++ b/src/gallium/drivers/radeonsi/radeonsi_pipe.c
@@ -117,7 +117,7 @@ static struct r600_fence *r600_create_fence(struct r600_context *rctx)
pipe_reference_init(&fence->reference, 1);
rscreen->fences.data[fence->index] = 0;
- r600_context_emit_fence(rctx, rscreen->fences.bo, fence->index, 1);
+ si_context_emit_fence(rctx, rscreen->fences.bo, fence->index, 1);
/* Create a dummy BO so that fence_finish without a timeout can sleep waiting for completion */
fence->sleep_bo = si_resource_create_custom(&rctx->screen->screen, PIPE_USAGE_STAGING, 1);
@@ -149,7 +149,7 @@ void radeonsi_flush(struct pipe_context *ctx, struct pipe_fence_handle **fence,
ctx->render_condition(ctx, NULL, 0);
}
- r600_context_flush(rctx, flags);
+ si_context_flush(rctx, flags);
/* Re-enable render condition. */
if (render_cond) {
@@ -206,10 +206,10 @@ static struct pipe_context *r600_create_context(struct pipe_screen *screen, void
rctx->family = rscreen->family;
rctx->chip_class = rscreen->chip_class;
- r600_init_blit_functions(rctx);
+ si_init_blit_functions(rctx);
r600_init_query_functions(rctx);
r600_init_context_resource_functions(rctx);
- r600_init_surface_functions(rctx);
+ si_init_surface_functions(rctx);
rctx->context.create_video_decoder = vl_create_decoder;
rctx->context.create_video_buffer = vl_video_buffer_create;
@@ -249,7 +249,7 @@ static struct pipe_context *r600_create_context(struct pipe_screen *screen, void
return NULL;
}
- r600_get_backend_mask(rctx); /* this emits commands and must be last */
+ si_get_backend_mask(rctx); /* this emits commands and must be last */
rctx->dummy_pixel_shader =
util_make_fragment_cloneinput_shader(&rctx->context, 0,
diff --git a/src/gallium/drivers/radeonsi/radeonsi_pipe.h b/src/gallium/drivers/radeonsi/radeonsi_pipe.h
index cca4f02f44..bec2939d3f 100644
--- a/src/gallium/drivers/radeonsi/radeonsi_pipe.h
+++ b/src/gallium/drivers/radeonsi/radeonsi_pipe.h
@@ -186,18 +186,18 @@ struct r600_context {
};
/* r600_blit.c */
-void r600_init_blit_functions(struct r600_context *rctx);
-void r600_blit_uncompress_depth(struct pipe_context *ctx, struct r600_resource_texture *texture);
+void si_init_blit_functions(struct r600_context *rctx);
+void si_blit_uncompress_depth(struct pipe_context *ctx, struct r600_resource_texture *texture);
void r600_blit_push_depth(struct pipe_context *ctx, struct r600_resource_texture *texture);
-void r600_flush_depth_textures(struct r600_context *rctx);
+void si_flush_depth_textures(struct r600_context *rctx);
/* r600_buffer.c */
-bool r600_init_resource(struct r600_screen *rscreen,
- struct si_resource *res,
- unsigned size, unsigned alignment,
- unsigned bind, unsigned usage);
-struct pipe_resource *r600_buffer_create(struct pipe_screen *screen,
- const struct pipe_resource *templ);
+bool si_init_resource(struct r600_screen *rscreen,
+ struct si_resource *res,
+ unsigned size, unsigned alignment,
+ unsigned bind, unsigned usage);
+struct pipe_resource *si_buffer_create(struct pipe_screen *screen,
+ const struct pipe_resource *templ);
void r600_upload_index_buffer(struct r600_context *rctx,
struct pipe_index_buffer *ib, unsigned count);
@@ -214,9 +214,7 @@ void r600_init_context_resource_functions(struct r600_context *r600);
/* r600_texture.c */
void r600_init_screen_texture_functions(struct pipe_screen *screen);
-void r600_init_surface_functions(struct r600_context *r600);
-unsigned r600_texture_get_offset(struct r600_resource_texture *rtex,
- unsigned level, unsigned layer);
+void si_init_surface_functions(struct r600_context *r600);
/* r600_translate.c */
void r600_translate_index_buffer(struct r600_context *r600,
diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c b/src/gallium/drivers/radeonsi/si_state_draw.c
index c865eecb61..76550c2bdc 100644
--- a/src/gallium/drivers/radeonsi/si_state_draw.c
+++ b/src/gallium/drivers/radeonsi/si_state_draw.c
@@ -354,7 +354,7 @@ static void si_update_derived_state(struct r600_context *rctx)
if (!rctx->blitter->running) {
if (rctx->have_depth_fb || rctx->have_depth_texture)
- r600_flush_depth_textures(rctx);
+ si_flush_depth_textures(rctx);
}
if ((rctx->ps_shader->shader.fs_write_all &&
@@ -551,7 +551,7 @@ void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info)
/* Emit states. */
rctx->pm4_dirty_cdwords += si_pm4_dirty_dw(rctx);
- r600_need_cs_space(rctx, 0, TRUE);
+ si_need_cs_space(rctx, 0, TRUE);
si_pm4_emit_dirty(rctx);
rctx->pm4_dirty_cdwords = 0;