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##
## This file is part of the coreboot project.
##
## Copyright (C) 2007-2009 coresystems GmbH
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
## GNU General Public License for more details.
##
## You should have received a copy of the GNU General Public License
## along with this program; if not, write to the Free Software
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##

config NORTHBRIDGE_AMD_AMDFAM10
	bool
	select HAVE_DEBUG_RAM_SETUP
	select HAVE_DEBUG_SMBUS
	select HAVE_DEBUG_CAR
	select HYPERTRANSPORT_PLUGIN_SUPPORT
	select MMCONF_SUPPORT
	select PER_DEVICE_ACPI_TABLES

if NORTHBRIDGE_AMD_AMDFAM10
config AGP_APERTURE_SIZE
	hex
	default 0x4000000

config HT3_SUPPORT
	bool
	default y

config AMDMCT
	bool
	default y

config HW_MEM_HOLE_SIZEK
	hex
	default 0x100000

config HW_MEM_HOLE_SIZE_AUTO_INC
	bool
	default n

config MMCONF_BASE_ADDRESS
	hex
	default 0xe0000000

config MMCONF_BUS_NUMBER
	int
	default 256

# TODO: Reservation for heap seems excessive
config HEAP_SIZE
	hex
	default 0xc0000

config RAMTOP
	hex
	default 0x400000

config BOOTBLOCK_NORTHBRIDGE_INIT
        string
        default "northbridge/amd/amdfam10/bootblock.c"

config SB_HT_CHAIN_UNITID_OFFSET_ONLY
	bool
	default n

config DIMM_FBDIMM
	bool
	default n

config DIMM_DDR2
	bool
	default n

config DIMM_DDR3
	bool
	default n

config DIMM_REGISTERED
	bool
	default n

if DIMM_FBDIMM
	config DIMM_SUPPORT
		hex
		default 0x0110
endif

if DIMM_DDR2
	if DIMM_REGISTERED
	config DIMM_SUPPORT
		hex
		default 0x0104
	endif

	if !DIMM_REGISTERED
	config DIMM_SUPPORT
		hex
		default 0x0004
	endif
endif

if DIMM_DDR3
	if DIMM_REGISTERED
	config DIMM_SUPPORT
		hex
		default 0x0005
	endif
endif

config SVI_HIGH_FREQ
	bool
	default n
        help
          Select this for boards with a Voltage Regulator able to operate
          at 3.4 MHz in SVI mode. Ignored unless the AMD CPU is rev C3.

endif # NORTHBRIDGE_AMD_AMDFAM10