aboutsummaryrefslogtreecommitdiffstats
path: root/src/arch/arm/verstage.ld
blob: 88d4bc8dfb03b00aa96b7a3b4d1f716aa72733fe (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
/*
 *	Memory map:
 *
 *	CONFIG_VERSTAGE_BASE	: text segment
 *				: rodata segment
 *				: data segment
 *				: bss segment
 */

/* We use ELF as output format. So that we can debug the code in some form. */
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
OUTPUT_ARCH(arm)

PHDRS
{
	to_load PT_LOAD;
}

ENTRY(stage_entry)

SECTIONS
{
	. = CONFIG_VERSTAGE_BASE;

	.romtext . : {
		_start = .;
		*(.text.stage_entry.arm);
		*(.text.startup);
		*(.text);
		*(.text.*);
	} : to_load

	.romdata . : {
		*(.rodata);
		*(.rodata.*);
		*(.data);
		*(.data.*);
		. = ALIGN(8);
	}

	/* bss does not contain data, it is just a space that should be zero
	 * initialized on startup. (typically uninitialized global variables)
	 */
	.bss . : {
		. = ALIGN(8);
		_bss = .;
		*(.bss)
		*(.bss.*)
		*(.sbss)
		*(.sbss.*)
		_ebss = .;
	}

	_end = .;

	preram_cbmem_console = CONFIG_CONSOLE_PRERAM_BUFFER_BASE;

	/* Discard the sections we don't need/want */
	/DISCARD/ : {
		*(.comment)
		*(.note)
		*(.comment.*)
		*(.note.*)
		*(.eh_frame);
	}
}