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* tegra124/nyan: rougly stable code baseGabe Black2014-09-1144-597/+4328
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | nyan: Clock setup. Reviewed-on: https://chromium-review.googlesource.com/172106 (cherry picked from commit 3697b6454c0aceebcf735436de90ba2441c9b7b1) tegra124: Call into the mainboard bootblock init if one exists. Reviewed-on: https://chromium-review.googlesource.com/172581 (cherry picked from commit 3a0cd48a0d1a9ce6b32ed614cd81fb81f5f82aec) nyan: Add a mainboard specific bootblock. Reviewed-on: https://chromium-review.googlesource.com/172582 (cherry picked from commit a83d065d660a26fe71ed79879c25f84a1b669f69) nyan: tegra124: Redestribute the clock code between the mainboard and soc. Reviewed-on: https://chromium-review.googlesource.com/172583 (cherry picked from commit ea703137fc37befa7d5a65afc982e298a0daca1b) nyan: Initialize the i2c pins and controllers. Reviewed-on: https://chromium-review.googlesource.com/172584 (cherry picked from commit 9c10a3074ef834688fea46c03551c2e3e54e44a8) nyan: Initialize the PMIC. Reviewed-on: https://chromium-review.googlesource.com/172585 (cherry picked from commit f6be8b0e607e05b73b5e4a84afcf04c879eee88a) tegra124: add a chip.h and use it in NYAN Reviewed-on: https://chromium-review.googlesource.com/172773 (cherry picked from commit 4dd5f1f091f2dcae5ce38203bb86c62994609f8f) tegra: Reorder GPIO register accesses to avoid glitching Reviewed-on: https://chromium-review.googlesource.com/172730 (cherry picked from commit 61bedbf0f839e19b284d21af2ad10f2ff15e17d5) tegra: Turn GPIO wrappers into macros to make them easier to write Reviewed-on: https://chromium-review.googlesource.com/172731 (cherry picked from commit 94550fdfa5a8005d2e6a313041de212ab7ac470c) tegra: Change GPIO functions to allow variable arguments Reviewed-on: https://chromium-review.googlesource.com/172916 (cherry picked from commit e95ccd984f718a04b6067ff6ad5049a2cd74466d) tegra124: Implement starting up the main CPUs. Reviewed-on: https://chromium-review.googlesource.com/172917 (cherry picked from commit 7c5169a197310e18a3df0f176c499669e3c2bda3) tegra: Simplify the I2C constants. Reviewed-on: https://chromium-review.googlesource.com/172953 (cherry picked from commit 130a07c86dfa5ba5ac4580f29db927c91f045c76) tegra124: Fix SPI base addresses Reviewed-on: https://chromium-review.googlesource.com/173322 (cherry picked from commit da808e46919ebd3b9f2377a5889f0d5f10b92357) tegra124: Scrub the clock constants. Reviewed-on: https://chromium-review.googlesource.com/172954 (cherry picked from commit 9305ff0696a6d556a97f928b8683770833a309a4) tegra124: add DMA support Reviewed-on: https://chromium-review.googlesource.com/172951 (cherry picked from commit 4d2a5a56b922ac37d2326d7b139697567aac37b8) tegra124: add basic SPI driver Reviewed-on: https://chromium-review.googlesource.com/172952 (cherry picked from commit 5f861f13c7fd2dd881f3cbd0f1b4d4a9994ce429) tegra124: Add an assembly stub which is run first on the main CPUs. Reviewed-on: https://chromium-review.googlesource.com/173541 (cherry picked from commit e142b9572a89f43fe984c4fc87e3203f380ff4de) nyan: tegra124: Set up dynamic cbmem. Reviewed-on: https://chromium-review.googlesource.com/173542 (cherry picked from commit b6e1a70103446abb5c3440f145617e6566879c6f) tegra124: Add an soc.c which sets up the chip operations and memory resource. Reviewed-on: https://chromium-review.googlesource.com/173543 (cherry picked from commit af49a5bd1f589cf053c4808510138aae26e20db4) tegra124: extend chip.h to include video settings Reviewed-on: https://chromium-review.googlesource.com/173600 (cherry picked from commit 87687633a2116f58fad7333b3b639cee9089ad29) tegra124 and nyan: fill in the devicetree a bit more, add defines Reviewed-on: https://chromium-review.googlesource.com/173684 (cherry picked from commit c107eaca3dea42be89f61690d0d6cb2181acb147) tegra124: clean-ups for SPI driver Reviewed-on: https://chromium-review.googlesource.com/173599 (cherry picked from commit 1e2f9fd442ea336bf0663c3c8ea51f771e21beb7) tegra124: add a #define for DMA alignment size Reviewed-on: https://chromium-review.googlesource.com/173638 (cherry picked from commit f9dc2a8d8016fa7db974fb6cb01c3275e26832af) tegra124: Add FIFO transmit functions to SPI driver Reviewed-on: https://chromium-review.googlesource.com/173639 (cherry picked from commit 97e61f36ad96ce2f9b12a7ef765ee73d3f4285f7) tegra124: clean-ups for DMA driver Reviewed-on: https://chromium-review.googlesource.com/173598 (cherry picked from commit 750c0a5d6942748dd21f3a3f884ad94a561e86e0) tegra124: early display and display code. Reviewed-on: https://chromium-review.googlesource.com/173622 (cherry picked from commit 651c7ab96b1f136865e4673a120de7afc1218558) tegra124: Move transfer size handling to spi_xfer() Reviewed-on: https://chromium-review.googlesource.com/173680 (cherry picked from commit 4a9b7b47b3c09d70063ea843054ffef98f554621) tegra124: strict error detection and reporting for SPI Reviewed-on: https://chromium-review.googlesource.com/173681 (cherry picked from commit c056fa954e1dab40a56faec6c50385763a2eb010) tegra124: add thread-friendly delays to SPI driver Reviewed-on: https://chromium-review.googlesource.com/173648 (cherry picked from commit c1a321c8f61942801627f895c5db74c518e2aa8e) Tegra124: Take the SPI1 controller out of reset and enable its clock. Reviewed-on: https://chromium-review.googlesource.com/173787 (cherry picked from commit c026a3fb861e157f1e17a121fc2ef70b903f36f2) tegra124: add two more clock setting values Reviewed-on: https://chromium-review.googlesource.com/173772 (cherry picked from commit 7d79d7dd9f0c1fd7127a7ba41652d809ccff7a57) nyan: Set up the ChromeOS related GPIOs and SPI bus 1 which goes to the EC. Reviewed-on: https://chromium-review.googlesource.com/173788 (cherry picked from commit ff172bfe30f75983a1e8efa2ead0a4519583d0a8) tegra124: Add some stub functions to the Tegra SPI driver. Reviewed-on: https://chromium-review.googlesource.com/173789 (cherry picked from commit 8bc527aa4afd301c046b0e844c7fa400630af0d2) tegra124: Build source files into the various stges needed by CONFIG_CHROMEOS. Reviewed-on: https://chromium-review.googlesource.com/173790 (cherry picked from commit 86a6423b668ca912295c47d8c6e3ef6c6f8c6084) nyan: Implement the code which reads GPIOs for ChromeOS. Reviewed-on: https://chromium-review.googlesource.com/173791 (cherry picked from commit 4c394dfbce762574fc79edcb6e4ac6bf346e48a3) nyan: Enable the CHROMEOS and ChromeOS EC related kconfig options. Reviewed-on: https://chromium-review.googlesource.com/173792 (cherry picked from commit 2845a4487159aa4b1dba58d977f52c449574fc8e) Tegra124: SDMMC: Take the SDMMC 3 and 4 out of reset and ungate their clocks. Reviewed-on: https://chromium-review.googlesource.com/173793 (cherry picked from commit c238b87bcd9d35afd828476d6ee88322ac5d0f88) tegra124: fix clear_fifo_status() in SPI driver Reviewed-on: https://chromium-review.googlesource.com/173738 (cherry picked from commit f415d2c0aaffc0f1a3592551a2db782d538f8f4f) ARM: Include stdint.h in cpu.h. Reviewed-on: https://chromium-review.googlesource.com/173774 (cherry picked from commit f1930faea3f14b2a2560a6c4058ef38532b6f1a6) tegra124: When setting up the main CPU, set its CPSR appropriately. Reviewed-on: https://chromium-review.googlesource.com/173775 (cherry picked from commit bc2ba9c15cfd22aeaca4f80b1d13a8b5e0178ead) tegra124: fix wrong names in clk_rst.h Reviewed-on: https://chromium-review.googlesource.com/173955 (cherry picked from commit 19dd9c85e4a3d1f77b23828bcbdd4bd8c2688b8d) tegra124: Fix up the PLLX divider table. Reviewed-on: https://chromium-review.googlesource.com/173778 (cherry picked from commit 3362cf3a7d6f5eaec879dda42323345922f6df17) tegra124: clock: Get rid of cpcon and dccon. Reviewed-on: https://chromium-review.googlesource.com/173779 (cherry picked from commit 08626ffac4a7e9ea3d4738af87e9e4cced7be2c7) Tegra124: SPI: Set and unset CS in spi_claim_bus and spi_release_bus. Reviewed-on: https://chromium-review.googlesource.com/173953 (cherry picked from commit a2df8f3a9c9c54c62d6ff37d3baff1d30ee6d355) armv7: expose dcache_line_bytes() in cache API Reviewed-on: https://chromium-review.googlesource.com/173975 (cherry picked from commit 6727f65702c7668fcb33848b4113bc3d3cc04e12) libpayload: expose dcache_line_bytes() in ARM cache API Reviewed-on: https://chromium-review.googlesource.com/174099 (cherry picked from commit 9387b02dff85b42944d95c3bccf59059c93fb4a9) armv4: add a stub for dcache_line_bytes() Reviewed-on: https://chromium-review.googlesource.com/173976 (cherry picked from commit 924f61ea895b9268c716791466637009bbac6469) tegra124: Base early UART on CLK_M to enable debugging of PLL init code Reviewed-on: https://chromium-review.googlesource.com/174339 (cherry picked from commit 8d9387432f0a0d9b257b040304238e543cced1aa) tegra124: Add additional PLLs and redesign the divisor table Reviewed-on: https://chromium-review.googlesource.com/174380 (cherry picked from commit f6a5f5c4562f1ca733505717c175be00413f2384) Squashed 49 commits for tegra124/nyan that included a lot of churn on different pieces. Change-Id: I00e8f5b74e835e01b28ca2e9c4af3709c9363d56 Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6869 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
* Move nehalem/sandy/ivy to per-device acpiVladimir Serbinenko2014-09-1132-2223/+150
| | | | | | | | Change-Id: I3d664ab575bf9c49a7bff9a395fbab96748430d0 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6802 Reviewed-by: Aaron Durbin <adurbin@google.com> Tested-by: build bot (Jenkins)
* mainboard/google/parrot: fix ACPI interrupt storm on lid switch changeAndrew Litt2014-09-111-0/+7
| | | | | | | | | | | | | | | | | This fixes the ACPI interrupt storm on Parrot that happens when closing the lid or entering suspend by lid close (seen in /sys/firmware/acpi/interrupts/gpe1F). This patch inverts the interrupt trigger level every time the interrupt is received so that it doesn't fire until the next state change. http://askubuntu.com/questions/310196 is a good example of what this is trying to solve. Change-Id: I8b095914e9330c3217a4ceb058613fa952f4a234 Signed-off-by: Andrew Litt <ajlitt@splunge.net> Reviewed-on: http://review.coreboot.org/6858 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@google.com>
* Increase space for ACPI tables when using dynamic CBMEMStefan Reinauer2014-09-111-0/+4
| | | | | | | | | | | | | | Unlike in old style CBMEM, dynamic CBMEM does not have a hand-calculated, hard-coded size, so allow up to 144K of space for ACPI tables. Change-Id: Id9dd7447c46d5fe7ed581be753d70e59add05320 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/6795 Tested-by: build bot (Jenkins) Reviewed-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
* roda/rk886ex: Move dummy DCC ON# to finalize stageStefan Reinauer2014-09-111-3/+9
| | | | | | | | | | | | | During Vladimir's ACPI cleanups, this was moved into the mainboard's enable stage, which will prevent the VGA option rom from executing correctly. Move it to the finalize stage to make sure it runs after all initialize functions have been called. Change-Id: I0fcca4d4a95f89382f377ce923f82ecb71467fd8 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/6845 Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com> Tested-by: build bot (Jenkins)
* tegra124: Make tegra124 compilable with serial turned off.Gabe Black2014-09-101-3/+5
| | | | | | | | | | | | | | | | | | The bootblock and romstage UART consoles were being built in based only on whether or not the bootblock and romstage consoles were selected, ignoring whether serial console support was compiled in generally. Change-Id: I3866519c422a990c44ced66885108eff24894563 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://chromium-review.googlesource.com/172580 Reviewed-by: Ronald Minnich <rminnich@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit a4f2dd4902a05884693e6e350b6be29276d16981) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6862 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
* nyan: Use the new pinmux functions as part of UART setup.Gabe Black2014-09-101-31/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The pins for the UART had been configured manually using hardcoded offsets and values. Now that we have pinmux functions for that sort of thing, we should use that instead. This also provides a very simple test for the pinmux code. Ultimately this code should be wrapped in a function which handles setting up any of the UARTs which is appropriately parameterized and which would be called from the bootblock main instead of being in it, but for now this is sufficient. Old-Change-Id: I69e36fa5fc9b6f3f5ef7f1be3e9f18cdbfdd7fe9 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://chromium-review.googlesource.com/171807 Reviewed-by: Ronald Minnich <rminnich@chromium.org> Reviewed-by: David Hendricks <dhendrix@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit d29e655b68143e86199ab1d74f89e125b16b67cc) tegra124: Call the set_avp_clock_to_clkm function in the bootblock. We had a hardcoded version of the set_avp_clock_to_clkm function in the bootblock, and we had to use it until now because the real version uses udelay, and until now that hadn't been implemented. Also, replace the delay loop in the hacky_hardcoded_uart_setup_function with a call to the real thing. Old-Change-Id: I6df9421bcad484e0855c67649683d474d78e4883 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://chromium-review.googlesource.com/172045 Reviewed-by: Gabe Black <gabeblack@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 4c6dd4c7cade7d922a258e0371e43972bce77249) Squashed two tegra124 bootblock related commits. Change-Id: I0ce6321a04b11b7f1250ef3816fe46732777988d Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6861 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
* Exynos5420: Fix up the i2c driver for use with the TPM driverGabe Black2014-09-101-13/+15
| | | | | | | | | | | | | | | | | | | | The TPM driver expects to call i2c_read with zero address length. The i2c driver wasn't prepared to handle that particularly in the case of reads because it expected to send an address before switching over to read mode for the data. This change also fixes up the read and write calls to consistently be read32 and write32 instead of readl and writel. Change-Id: I33dee89b83d4cd9d3e1b90e84b40e761bb8d4de4 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://chromium-review.googlesource.com/175966 Reviewed-by: Stefan Reinauer <reinauer@chromium.org> Tested-by: Stefan Reinauer <reinauer@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> (cherry picked from commit cf686269424ea938d6f953d0f76103182eb71297) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6857 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
* samus: Fix 8GB SPDDuncan Laurie2014-09-102-2/+2
| | | | | | | | | | | | | | | The 8GB variant is x16 with 11 column bits and 4Gb density. Change-Id: I3aa647aba88dbc928fefd826cbd01e4fa8273660 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/176640 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Commit-Queue: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit d18462f6fc0d40328e9619525240778ea6b1a426) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6856 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
* tpm: Clean up I2C TPM driverStefan Reinauer2014-09-1012-819/+687
| | | | | | | | | | | | | | | | | | Drop a lot of u-boot-isms and share common TIS API between I2C driver and LPC driver. Signed-off-by: Stefan Reinauer <reinauer@google.com> Change-Id: I43be8eea0acbdaef58ef256a2bc5336b83368a0e Reviewed-on: https://chromium-review.googlesource.com/175670 Commit-Queue: Stefan Reinauer <reinauer@chromium.org> Tested-by: Stefan Reinauer <reinauer@chromium.org> Reviewed-by: David Hendricks <dhendrix@chromium.org> (cherry picked from commit 3fc8515b9dcef66998658e1aa5c020d22509810c) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6855 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
* samus: GPIO updates for Proto1bDuncan Laurie2014-09-102-17/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move NFC_INT to GPIO9 Swap CODEC_INT to GPIO46 and WLAN_DISABLE_L to GPIO42 Swap ACCEL_INT to GPIO45 and PP1800_CODEC_EN to GPIO43 Enable PP1800_CODEC_EN, CODEC_LDOENA, CODEC_RESET_L Old-Change-Id: I5547d34f1b7953808375aa5fe5e0a9640ae7e05e Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/175291 Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 5bb4bc59e37ee4fe9a0556e08a53402c822e5bd6) samus: Misc fixes from proto1b bringup - NFC interrupt is expected in the kernel as a GPIO now, so set it back to that type - NFC FW update GPIO should be low - Accel/Codec interrupts were still set as GPIO type, they should be set as PIRQ type Old-Change-Id: I354c848ae7b158943f4745872b82a49e17e67e2f Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/176513 Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 75a0944f320c80618f12732a23344ce40010a688) Squashed two small patches for samus. Change-Id: I7ec56191fe2b7f19e470df175ad0bbe320a442f5 Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6852 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
* nyan: Add a stub mainboard.Gabe Black2014-09-1011-0/+579
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Old-Change-Id: Icdde4cf5e1abb3ae1ad14279ebc129919ba30074 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://chromium-review.googlesource.com/170837 Reviewed-by: Gabe Black <gabeblack@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit e9d87534ccacb42d508f1902786470798a2dbaea) nyan: Add a "special-class" for aggregating BCT files into bct.cfg. The config file which cbootimage processes to create a BCT could come from multiple different files, individually selected based on config options, and/or split up into different files for organizational purposes. This change adds a special-class which collects those files and concatenates them all together in a bct.cfg which can be processed more easily by other parts of the build. While the BCT files themselves are potentially very board specific, for instance ones that hold memory timing information, this bit of code which collects them is not. It has to be in each board file instead of alongside the CPU, however, to ensure that the special class is set up before another Makefile tries to use it. If we end up with lots of Tegra based boards which duplicate this code over and over, we might want to revisit how this works. Old-Change-Id: I58e1373434f89e69298990ea4643a19d8afdc309 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://chromium-review.googlesource.com/170922 Reviewed-by: Gabe Black <gabeblack@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 3ae44178b7084037a75e16ce161b1432abf4246a) nyan: Add bct files for nyan. There's a config option which selects between the emmc and spi config files depending on what the firmware is intended to boot from. These are copied from the files installed by the tegra-bct-nyan ebuild, except that the spi config file has been modified so that there's only one copy of the BCT and so that it only has one configuration. This is to save space in the final image. Old-Change-Id: Ibf1b895bb3ed060d394fc6ffcec67b6972bb21e3 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://chromium-review.googlesource.com/170923 Reviewed-by: Gabe Black <gabeblack@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 6bbcffe04e8ae73c86bc05c577a67f909857e1c0) Squashed three commits required to get nyan building since some patches were out of order. Added a select to the nyan mainboard Kconfig to have a rom size of 1024K to match the saved config on the chromium side. Change-Id: I346dbb02d216adfea9707e40adf0a4d1e0fabf36 Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6669 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
* nvidia-cbootimage: integrate into coreboot makeIsaac Christensen2014-09-101-4/+2
| | | | | | | | | | | | Add rules for building the nvidia-cbootimage utility and add dependencies to the tegra124 platform. Change-Id: Ia9f26981bccd217fe79e1b5dd432ee7da868d22a Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6851 Reviewed-by: Aaron Durbin <adurbin@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
* lenovo/t520/acpi/gpe.asl: fix ExpressCard gpe configExpreNicolas Reinecke2014-09-101-5/+5
| | | | | | | | | | | ExpressCard is connected to PCIe port 4. Change-Id: I0cffabd9d9435d24a7e9c178c2f96fb1a9390320 Signed-off-by: Nicolas Reinecke <nr@das-labor.org> Reviewed-on: http://review.coreboot.org/6850 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* lenovo/t520/hda_verb.h: update azalia codec configNicolas Reinecke2014-09-101-81/+19
| | | | | | | | | | | | | | Replace codec config copied form T530 with dumped values from T520 /sys/class/sound/card0/hdaudioC0D0/init_pin_configs. Intel Azalia HDMI is always enabled, but DP isn't connected to a connector. Change-Id: Iabdae4a6669ff429d5769a1bb0c0fb1abc12ba82 Signed-off-by: Nicolas Reinecke <nr@das-labor.org> Reviewed-on: http://review.coreboot.org/6849 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins)
* lenovo/t520/gpio.h: Fix current gpio configurationNicolas Reinecke2014-09-101-19/+18
| | | | | | | | Change-Id: I67f321583211efd9ed917276cc3989c6dc4ac649 Signed-off-by: Nicolas Reinecke <nr@das-labor.org> Reviewed-on: http://review.coreboot.org/6848 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins)
* arm: Update a stale comment in bootblock .S filesDavid Hendricks2014-09-093-3/+3
| | | | | | | | | | | | | | | | | | This just updates a comment which refers to "board_init_f". We use bootblock main() in coreboot. Change-Id: I4cb6b3c11f163b67fe48de495d13dce88710efc0 Reviewed-on: https://chromium-review.googlesource.com/172095 Reviewed-by: Gabe Black <gabeblack@chromium.org> Commit-Queue: David Hendricks <dhendrix@chromium.org> Tested-by: David Hendricks <dhendrix@chromium.org> (cherry picked from commit 65139f29682cedca8dfb58b3dfe67eab64299064) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6791 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins)
* exynos: Install the BL1 and set the checksum in the Makefile.Gabe Black2014-09-095-39/+24
| | | | | | | | | | | | | | | | | | | | | Install the BL1 and set up the checksum in the Makefile instead of relying on post processing. Import the exynos checksum script, split it in two and simplify it significantly. Stop putting the CBFS header in the midst of the bootblock so that it can be checksummed before CBFS is put together. Stop saving space for it and leaving an anchor in the bootblock which nobody looks for. Change-Id: Icbb5a5914ece60b2827433b6dc29d80db996ea6c Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://chromium-review.googlesource.com/179229 Reviewed-by: Ronald Minnich <rminnich@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit aa3a416705517c0a6ddfdeb19905ac8cafb33df1) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6834 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* ARMv4: Add a minimal version of cpu.h.Gabe Black2014-09-091-0/+25
| | | | | | | | | | | | | | | | | | | All this version does is define asmlinkage to be nothing. It's required by the threading header file which is brought in by the timer implementation which I think is the hook for thread switching. Change-Id: Id57261d7c2c5ff8be00b0ad71bf7aaa9f3e24c1d Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://chromium-review.googlesource.com/171801 Reviewed-by: Ronald Minnich <rminnich@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> (cherry picked from commit e00379f54802066fd3e0685b291cdec289078055) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6831 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
* tegra124: Switch the bootblock over the ARMv4 impelementation.Gabe Black2014-09-092-4/+1
| | | | | | | | | | | | | | | | | The bootblock for the tegra124 runs on the AVP coprocessor which uses the ARMv4 architecture. Switch it over to that architecture. Change-Id: Ie527bbff938e6148c58727d448f9c2e6862da872 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://chromium-review.googlesource.com/171402 Reviewed-by: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> (cherry picked from commit c1aa76b7607ee40ff848628971a97eea5393aebe) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6784 Reviewed-by: Marc Jones <marc.jones@se-eng.com> Tested-by: build bot (Jenkins)
* ARM: Add an ARMv4 architecture version.Gabe Black2014-09-099-1/+450
| | | | | | | | | | | | | | | | | | | This is needed for the tegra124's bootblock and includes enough implementation to support that use. No caching is supported, although there are function prototypes and stub implementations to satisfy includes and linking. Change-Id: Ib79dde8c30eda98b3e823cba2ff6115a610bb2e8 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://chromium-review.googlesource.com/171401 Reviewed-by: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 221dc76b3ce4c1d73851c432333e091e1c60f0cb) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6783 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
* getac/p470: Add some more board info dataPatrick Georgi2014-09-091-0/+2
| | | | | | | | | Change-Id: I7cf47a16928436734df29af951f987db9cf9530d Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/6847 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
* Haswell/falco/peppy/slippy: continue to clean up FUI.Ronald G. Minnich2014-09-089-194/+76
| | | | | | | | | | | | | | | | | | | | | | | | As a first step towards removing hardcodes from the FUI support, change the haswell call to i915_lightup to panel_lightup, and pass the intel_dp * as a parameter. Get rid of the scalar arguments and make them part of intel_dp. Get rid of file-scope variables and use the ones in the intel_dp struct. In falco, use functions that peppy uses. Drop slippy support for FUI, it's a dead board; if this is ok I'll remove the files next. And, incidentally, fix the broken RGBX constant and change it to BGRX. Change-Id: I46ef5a9ed8433382d042066ee3542af04cfc319a Signed-off-by: Ronald G. Minnich <rminnich@google.com> Reviewed-on: https://chromium-review.googlesource.com/174932 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Commit-Queue: Ronald Minnich <rminnich@chromium.org> Tested-by: Ronald Minnich <rminnich@chromium.org> (cherry picked from commit 1e1ed410b445c8e2b7411e163d9d6f61499dc3f6) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6833 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
* FALCO: stop using the slippy graphics codeRonald G. Minnich2014-09-083-1/+525
| | | | | | | | | | | | | | | | | It's time to start cleaning up the falco graphics code, but it needs to have its own files, not slippy's. Change-Id: I7dbe27eafbf247b5c7806819bf0059d8b10e842c Signed-off-by: Ronald G. Minnich <rminnich@google.com> Reviewed-on: https://chromium-review.googlesource.com/172501 Tested-by: Ronald Minnich <rminnich@chromium.org> Reviewed-by: Stefan Reinauer <reinauer@google.com> Commit-Queue: David Hendricks <dhendrix@chromium.org> (cherry picked from commit 262a0c16a39871d14972a92bff2dbc24de2ca3f0) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6832 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* samus: Disable SMBus controllerDuncan Laurie2014-09-081-1/+1
| | | | | | | | | | | | | | | Nothing is connected to this port. Change-Id: If3e466a3053fa694a511c2335c16381f77f56f47 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/174089 Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 5ddb6a444d5c3141868eaf618ecb014b0262a796) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6827 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
* tegra124: return the UART base address based on indexIsaac Christensen2014-09-081-2/+11
| | | | | | | | Change-Id: I73a8e56559c7ffdaab39a5c19311221c91565004 Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6830 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* samus: Tweaks from bringupDuncan Laurie2014-09-083-30/+9
| | | | | | | | | | | | | | | | | | | - GPIO29 is no longer connected so we don't need the SMI workaround on the entry to sleep states. - Disable touchscreen wake source until the kernel driver is working so it does not wake immediately. - Update a few GPIOs and disable the codec for now as it is leaking into the 1.8V DDR rail. Change-Id: Ia67b17eb4a097627befd8f39aadc939da1bf3d40 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/174122 Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 0fdc9a83a434378499f825d072ce0adba5ffda59) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6829 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* samus: Fix up memory SPD informationDuncan Laurie2014-09-087-42/+43
| | | | | | | | | | | | | | | | | | | | | The LPDDR3 memory is x32 and dual rank with 14 row bits. In addition the memory is actually elpida, even though they are owned by micron it is confusing to label it as such. And the ram strap options were inverted from what I expected so the memory table needs to be updated. Change-Id: Ia29a23e8140d884fb84f940806f041b40562aab9 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/174121 Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 0d63d36b8035165f95db798ed40488519e622a65) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6828 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* samus: Add onboard device configurationDuncan Laurie2014-09-082-4/+75
| | | | | | | | | | | | | Change-Id: Ib7b6688982e9f74cffe40d11d4a9ec69acd55d37 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/174088 Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 41624b073fb59b1372ee5a8eba3ed64c7e633311) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6826 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
* samus: Change thermal behavior to match other haswell platformsDuncan Laurie2014-09-083-88/+40
| | | | | | | | | | | | Change-Id: Ia835f16b156949f1841210c4a469223d5df28a54 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/174087 Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 8e51d1d74cdcadde9cbf10e8321d601b099c46bc) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6825 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* ARM: Generalize armv7 as arm.Gabe Black2014-09-0851-107/+208
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There are ARM systems which are essentially heterogeneous multicores where some cores implement a different ARM architecture version than other cores. A specific example is the tegra124 which boots on an ARMv4 coprocessor while most code, including most of the firmware, runs on the main ARMv7 core. To support SOCs like this, the plan is to generalize the ARM architecture so that all versions are available, and an SOC/CPU can then select what architecture variant should be used for each component of the firmware; bootblock, romstage, and ramstage. Old-Change-Id: I22e048c3bc72bd56371e14200942e436c1e312c2 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://chromium-review.googlesource.com/171338 Reviewed-by: Gabe Black <gabeblack@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 8423a41529da0ff67fb9873be1e2beb30b09ae2d) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> ARM: Split out ARMv7 code and make it possible to have other arch versions. We don't always want to use ARMv7 code when building for ARM, so we should separate out the ARMv7 code so it can be excluded, and also make it possible to include code for some other version of the architecture instead, all per build component for cases where we need more than one architecture version at a time. The tegra124 bootblock will ultimately need to be ARMv4, but until we have some ARMv4 code to switch over to we can leave it set to ARMv7. Old-Change-Id: Ia982c91057fac9c252397b7c866224f103761cc7 Reviewed-on: https://chromium-review.googlesource.com/171400 Reviewed-by: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 799514e6060aa97acdcf081b5c48f965be134483) Squashed two related patches for splitting ARM support into general ARM support and ARMv7 specific pieces. Change-Id: Ic6511507953a2223c87c55f90252c4a4e1dd6010 Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6782 Tested-by: build bot (Jenkins)
* Implement ACPI in a per device wayVladimir Serbinenko2014-09-054-2/+162
| | | | | | | | | | | | This approach avoids having same basic tables 150-lines mantra over 100 times in codebase. Change-Id: I76fb2fbcb9ca0654f2e5fd5d90bd62392165777c Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6801 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Aaron Durbin <adurbin@google.com>
* Consolidate intel vga int15 hooksVladimir Serbinenko2014-09-0564-2298/+263
| | | | | | | | Change-Id: I9366dded98bf15f6da44ce893dd10698ba09fd55 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6820 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
* i82801gx: Kill unused TCG and SMI1Vladimir Serbinenko2014-09-054-50/+4
| | | | | | | | | | | SMI1 is being written to but never read from. Change-Id: I82c0800713e3093eb1317b5e1f6f228771134857 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6808 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* roda/rk886ex: Move device changes to mainboard code from acpi tables codeVladimir Serbinenko2014-09-052-4/+3
| | | | | | | | | Change-Id: I3d694e5b3092d78bce89f6baa7b2dedffddf3012 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6807 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
* azalia: Use convenience macros throughoutVladimir Serbinenko2014-09-0546-1378/+451
| | | | | | | | Change-Id: Ic044bf155bfcf93fa7cf3afd7287b7d0b615ef6d Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6839 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* azalia: Change specific PIN_CFGs to generic AZALIA_PIN_CFGVladimir Serbinenko2014-09-054-56/+32
| | | | | | | | Change-Id: I3463d0c283793547b00a7628f27f2f1777c21238 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6838 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* azalia: Add convenience macrosVladimir Serbinenko2014-09-051-0/+12
| | | | | | | | Change-Id: Ie605efdda3b486ae6ef780266e6c651e41bb5392 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6837 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* mainboard: Add AMD DB-FT3b (Olive Hill+) with Steppe Eagle SoCBruce Griffith2014-09-0429-0/+2970
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Create a new mainboard based on the AMD DB-FT3 development board (Olive Hill) using an AMD Steppe Eagle processor. The actual DB-FT3 and DB-FT3b mainboards are identical except for the soldered-down SoC device. The new AMD DB-FT3b development board (Olive Hill+) features: * Mini-ITX form factor * 2x DisplayPort * 1x VGA * Integrated Realtek RTL8111-compatible Ethernet * 2x USB 3.0 ports * 2x USB 2.0 externally-accessible ports * 2x USB 2.0 internally-accessible ports (via headers) * micro LPC header * Integrated platform security processor * 2x Full-size DDR3 DIMM support (1 channel) * Realtek ALC272 HD audio * 2x SATA ports * 1x SD card slot * 1x PCIe (x4) slot * 1x mini-PCIe slot * 8-pin programming header Eliminate the extraneous headers included in PlatformGnbPcie. BiosCallOuts normally has a bunch of extraneous references to the mainboard name. Rather than correct the spelling of a bunch of instances, just get rid of them. For the most part, use the Olive Hill ACPI definitions since the DB-FT3b board ("Olive Hill+") and Olive Hill are the same board with different processors. Change some function prototypes for functions without parameters to void instead of AGESA's VOID. There are no parameters for these functions, so there is no real reason to use VOID. S3 and fan control are not supported. HD audio is not working. Change-Id: I794d7a8f4f948346cfe7cbd443c9aed5f70c99ed Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com> Reviewed-on: http://review.coreboot.org/6681 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <gaumless@gmail.com>
* AMD Steppe Eagle: Disable "No Snoop Enable" to stop HDMI audio stutterBruce Griffith2014-09-041-2/+8
| | | | | | | | | | | | | | | Ubuntu's HDMI audio has noise and echo. Disable NoSnoopEnable can resolve this issue. The posted amd_late_init.c northbridge code is missing a test for Steppe Eagle northbridges. See coreboot Gerrit change 3934, commit ID 4ca721399c (AMD Olive Hill: Disable NoSnoopEnable to fix HDMI audio corruptions with Ubuntu). Change-Id: I89894d0ce4ad72ea16d61b445edb9e67920bca24 Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com> Reviewed-on: http://review.coreboot.org/6822 Tested-by: build bot (Jenkins) Reviewed-by: WANG Siyuan <wangsiyuanbuaa@gmail.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
* drivers/gma: remove unused codeRonald G. Minnich2014-09-042-230/+7
| | | | | | | | | | | | | | | | | | | | We had brought this code in from the kernel but found it best to use mainboard- or chipset specific versions. Firmware should strive to be as non-generic as possible. Change-Id: Ic1ca746cc52c3f9ea4de6895f2b32946229beada Signed-off-by: Ronald G. Minnich <rminnich@google.com> Reviewed-on: https://chromium-review.googlesource.com/172625 Tested-by: Ronald Minnich <rminnich@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Commit-Queue: Ronald Minnich <rminnich@chromium.org> Reviewed-by: Stefan Reinauer <reinauer@google.com> (cherry picked from commit 7dba0dfd25bf9e367f9e5128b15edb018e958c3a) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6779 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
* acpigen: Correctly handle root scopeVladimir Serbinenko2014-09-021-1/+6
| | | | | | | | Change-Id: I9b3c9109b01e348259e64e93a4397212216ab152 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6799 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
* smbios.c: Fix mismerge which led to laptop being default typeVladimir Serbinenko2014-09-021-1/+1
| | | | | | | | Change-Id: I97ccd08a5e7f094908ed3a85ddae53b158124995 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6823 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
* acpi_tables: Remove roda-specific access to 60f [copy-paste error]Vladimir Serbinenko2014-09-025-20/+0
| | | | | | | | Change-Id: I12ce0dda823d7733c473ed5ef3b0470d95d794ae Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6805 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
* google/link: Use common i915_reg.h.Vladimir Serbinenko2014-09-014-4126/+9
| | | | | | | | | | | | Checked by comparing binaries and seeing no differences other than build info. Change-Id: Ie702c540a18b50d6da0379f7c4e65adf3e4f18d4 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6819 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
* stout: Kill dead i915 filesVladimir Serbinenko2014-09-013-7300/+0
| | | | | | | | | | | Not referenced anywhere. Change-Id: I6529f2ecbc34a2fa9ca720fea1224670eb98bdcd Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6815 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
* lenovo/x60: Remove leftover declarationVladimir Serbinenko2014-09-011-3/+0
| | | | | | | | Change-Id: I1ab2118a3127dfacef6a389abd59050493e640fb Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6817 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
* samus: Change SPD to indicate LPDDRDuncan Laurie2014-08-314-4/+4
| | | | | | | | | | | | | | | | There is some magic new SPD SDRAM type 241 to indicate LPDDR. I cannot find it specificed in any JEDEC document but it is what the reference code uses. Change-Id: I21d7a943784435cb336ecdba7ca5eac0bf5fcd92 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/171900 Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 0a1385515c62fd1e534b12568df8aaf2170e06f4) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6777 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
* lenovo/x200: Kill access to nonexisting device [copy-paste error]Vladimir Serbinenko2014-08-311-1/+1
| | | | | | | | Change-Id: I1be939e870e8792f5ebb23623fe8f7f119adec36 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6806 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
* iWRainbowG6: Kill unused fileVladimir Serbinenko2014-08-311-42/+0
| | | | | | | | | Change-Id: I7b9b91519d87d70405b57920b3f1ab98c50526d1 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6810 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>