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* Rename {CPU|NB|SB}/amd/*_wrapper foldersefdesign982011-06-221-445/+0
| | | | | | | | | | | | | | | | | This change renames the cpu/amd/agesa_wrapper, northbridge/ amd/agesa_wrapper, and southbridge/amd/cimx_wrapper folders to {cpu|NB}/amd/agesa and {SB}/amd/agesa to shorten and simplify the folder names. There is also a fix to vendorcode/amd/agesa/lib/amdlib.c to append "ull" to a trio of 64-bit hexadecimal constants to allow abuild to run successfully. Change-Id: I2455e0afb0361ad2e11da2b869ffacbd552cb715 Signed-off-by: Frank Vibrans <frank.vibrans@amd.com> Signed-off-by: efdesign98 <efdesign98@gmail.com> Reviewed-on: http://review.coreboot.org/51 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
* ASRock E350M1: Configure SB800 GPP ports to support onboard pcie nicScott Duplichan2011-06-191-20/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | Scott Duplichan's patch from the mailing list: sb800 cimx wrapper: Run the complete sb800 cimx sbBeforePciInit() function once, after determining device 0x15 function enables. 1) Update the asrock e350m1 devicetree.cb to match the hardware. 2) Change the way the sb800 cimx wrapper code works. The original cimx code calls sb800 cimx function sbBeforePciInit() once. When ported to coreboot, the gpp component of this function was called once for each gpp port, as the gpp port's enable/disable state became known. A 05/15/2011 change makes the early gpp code run only once, triggered by processing the 4th gpp port. This method is not general enough because the 4th gpp port is not enabled on all boards. With the current change, the early gpp code runs when the first gpp port is processed. If any gpp ports are enabled, the first must be enabled. Tested with Win7 and linux on asrock e350m1. This change will also affect amd inagua, and has not been tested on that board. Change-Id: I93d44c216bfcab3c3a8fbb79d23dab43a65850e6 Signed-off-by: Scott Duplichan <scott@notabs.org> Acked-by: Marshall Buschman <mbuschman@lucidmachines.com> Reviewed-on: http://review.coreboot.org/44 Tested-by: build bot (Jenkins) Reviewed-by: Cristian Măgherușan-Stanciu <cristi.magherusan@gmail.com>
* trivial remove blanks at the end of lineKerry She2011-06-011-2/+2
| | | | | | | | Signed-off-by: Kerry She <kerry.she@amd.com> Acked-by: Kerry She <kerry.she@amd.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6614 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* This patch fix a AMD sb800 wrapper compile warning:Kerry She2011-06-011-6/+6
| | | | | | | | | | | src/southbridge/amd/cimx_wrapper/sb800/late call clear_ioapic but not include the prototype declare header file. Signed-off-by: Kerry She <kerry.she@amd.com> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6613 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* cimx_wrapper/sb800: Fix indent in late.c:sb800_enable()Peter Stuge2011-05-161-7/+7
| | | | | | | | Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6597 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Update gpp port configuration.Scott Duplichan2011-05-151-7/+7
| | | | | | | | | Signed-off-by: Scott Duplichan <scott@notabs.org> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6592 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Program the I/O APIC ID.Scott Duplichan2011-05-151-0/+19
| | | | | | | | | Signed-off-by: Scott Duplichan <scott@notabs.org> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6580 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Enable AHCI mode and hide IDE controller to reduce boot time.Scott Duplichan2011-05-151-2/+1
| | | | | | | | | | | Note: enable AHCI in seabios and apply seabios patch: http://www.mail-archive.com/seabios@seabios.org/msg00437.html Signed-off-by: Scott Duplichan <scott@notabs.org> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6579 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* This code provides southbridge initialization for SB800 south bridges. It ↵Frank Vibrans2011-02-141-0/+436
| | | | | | | | | | | | is dependent on the AMD CIMx/SB800 code. Signed-off-by: Frank Vibrans <frank.vibrans@amd.com> Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6346 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* remove the code which is not ready to release.Zheng Bao2011-01-181-425/+0
| | | | | | | | | Signed-off-by: Zheng Bao <zheng.bao@amd.com> Acked-by: Zheng Bao <zheng.bao@amd.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6263 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* AMD SB800: Drop component prefix from filenames.Uwe Hermann2011-01-011-0/+425
We did the same with other chipsets in r6150. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6236 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1