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* chromeec: lpc: Add variant MEC IOShawn Nematbakhsh2015-04-221-0/+6
| | | | | | | | | | | | | | | | | | | | MEC cannot access memmap-range data directly though LPC and instead must access through its EMI unit. BUG=chrome-os-partner:38224 TEST=Verify host command functionality on glower. BRANCH=None Change-Id: If98d425014a894ddeafad4268f92af5860878522 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 58ed3c50ab97ca1e172d5cdc00f4cd8e069e565c Original-Change-Id: I32b897836d28ef4f3b3aa5f81b9023f2ceb629c8 Original-Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/263611 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/9910 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* chromeec: Support accessing memmap data over port 62/66Shawn Nematbakhsh2015-04-221-1/+9
| | | | | | | | | | | | | | | | | | | | | | Some platforms cannot access the 900h-9ffh region over the LPC bus, so it's necessary to access memmap data over the ACPI cmd / data ports. BUG=chrome-os-partner:38224 TEST=Manual on Samus. Define EC_GOOGLE_CHROMEEC_ACPI_MEMMAP. Verify system boots cleanly and battery status is updated immediately on plug / unplug. BRANCH=None Change-Id: Ifbed938668d3770750a44105e40fccb9babf62ed Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 14762261a6a32b2e96ee835e852b2c9537436ae3 Original-Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Original-Change-Id: Idb516ff60b973d8833a41c45eac5765dafb8ec6d Original-Reviewed-on: https://chromium-review.googlesource.com/262314 Original-Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: http://review.coreboot.org/9886 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* chromeec: Add wakeup delay after SPI /CS assertionDavid Hendricks2015-04-021-0/+7
| | | | | | | | | | | | | | | | | | | | | | | Some ECs may require a few microseconds to ramp up their clock after being awaken by /CS assertion. This adds a Kconfig variable that can be overridden at the mainboard-level which will force a delay between asserting /CS and beginning a transfer. BUG=chrome-os-partner:32223 BRANCH=none TEST=verified ~100us delay using logic analyzer Change-Id: I6d9b8beaa808252f008efb10e7448afdf96d2004 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: ec6b10e4e3f0362dea0dc8046cfd4e4615a42585 Original-Change-Id: Ibba356e4af18f80a7da73c96dadfda0f25251381 Original-Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/220242 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-by: Alexandru Stan <amstan@chromium.org> Reviewed-on: http://review.coreboot.org/9217 Reviewed-by: David Hendricks <dhendrix@chromium.org> Tested-by: build bot (Jenkins)
* chromeec: provide proto v3 over i2c supportAaron Durbin2015-03-211-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | Certain boards need to speak proto v3 over i2c. Leverage the transport agnostic API to share the logic with other proto v3 impelementations. BUG=chrome-os-partner:31148 BRANCH=None TEST=Built and ran on ryu. Can talk to the EC successfully. Change-Id: I1d0cd6907057af4ded3c4460193bbe1d897a1db7 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: cb9ac965ad04c9491f40fd9aa595176a28a467b3 Original-Change-Id: Ib699120fd232392e8caa0889c2bf40f4587a8a35 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/211139 Original-Reviewed-by: Stefan Reinauer <reinauer@google.com> Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/8828 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* chromeec: Move SERIQ mode to LPC optionMarc Jones2015-03-181-1/+1
| | | | | | | | | | | | SERIRQ_CONTINUOUS_MODE is specific feature of LPC busses. This fixes a KCONFIG unmet dependency warning on ARM mainboards with chromeec. Change-Id: Iae61986219585dcb1124cf3b24fa32a8596d56c8 Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/8665 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* ec/google: Support ChromeOS EC on SPI bus.Hung-Te Lin2013-07-101-2/+16
| | | | | | | | | | | | | For devices with ChromeOS EC on SPI bus, use the standard SPI driver interface (see spi-generic.h) to exchange data. Note: Only EC protocol v3 is supported for SPI bus. Change-Id: Ia8dcdecd125a2bd7424d0c7560e046b6d6988a03 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: http://review.coreboot.org/3751 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* slippy/falco/peppy: Enable SERIRQ continuous modeDuncan Laurie2013-07-101-0/+1
| | | | | | | | | | | The Chrome EC still does not tolerate SERIRQ in quiet mode and so the keyboard does not work properly. Change-Id: I9ab052187c9926ce0e2c86b86dfe987dd6564c1b Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/3745 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* ChromeEC: Fix the default, depends for EC_GOOGLE_CHROMEEC_I2C.Gabe Black2013-07-101-2/+2
| | | | | | | | | | | | | The default for this variable should be n, it should only depend on EC_GOOGLE_CHROMEEC, and it should be (and is) explicitly enabled when needed. This prevents it from being turned on when the EC bus is SPI. Change-Id: Idc6651a764be4f055341a36b9b4a58990f050b0c Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3737 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* ChromeEC: Drop unneeded Kconfig variable EC_GOOGLE_API_ROOTStefan Reinauer2013-04-181-7/+0
| | | | | | | | | | | | | | | | This used to contain the path for the EC include files, but those files are included in coreboot now. Signed-off-by: Stefan Reinauer <reinauer@google.com> Change-Id: I4fce9831c5e21b0a69a6295dbda2580e1ca83369 Reviewed-on: https://gerrit.chromium.org/gerrit/47606 Reviewed-by: Randall Spangler <rspangler@chromium.org> Commit-Queue: Stefan Reinauer <reinauer@google.com> Tested-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/3057 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
* ec/google: Support Google's Chrome EC on I2C interface.Hung-Te Lin2013-04-161-2/+18
| | | | | | | | | | | | | | | | | | | | | | Google's Chrome EC can be installed on LPC or I2C bus, using different command protocol. This commit adds I2C support for devices like Google/Snow. Note: I2C interface cannot be automatically probed so the bus and chip number must be explicitly set. Verified by booting Google/Snow, with following console output: Google Chrome EC: Hello got back 11223344 status (0) Google Chrome EC: version: ro: snow_v1.3.108-30f8374 rw: snow_v1.3.128-e35f60e running image: 1 Change-Id: I8023eb96cf477755d277fd7991bdb7d9392f10f7 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: http://review.coreboot.org/3074 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
* ec/google: Isolate EC bus protocol implementation.Hung-Te Lin2013-04-121-0/+7
| | | | | | | | | | | | | | | | | The Chrome EC can be connected by different types of bus like LPC / I2C / SPI, and the current implementation is only for LPC. To support other types, we must first isolate the LPC protocol stuff and add configuration variable (EC_GOOGLE_CHROMEEC_LPC) to specify bus type. Verified by building google/link (with chromeec) configuration successfully. Change-Id: Ib2920d8d935bcc77a5394e818f69e9265e26e8a0 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: http://review.coreboot.org/3068 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
* Add support for Google ChromeECStefan Reinauer2013-02-221-0/+11
Google ChromeEC is an EC with completely open source firmware. See https://gerrit.chromium.org/gerrit/gitweb?p=chromiumos/platform/ec.git;a=summary for the EC firmware source code (aka more information about the ChromeEC) This patch adds support for the ChromeEC on coreboot's side. Great thanks to the ChromeEC team for this amazing work. It's another important milestone towards a free and open firmware stack on modern hardware. Change-Id: Iace78af9d291791d2f5f80ccca1587b418738cec Signed-off-by: Stefan Reinauer <reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/2481 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin.roth@se-eng.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>