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* Remove address from GPLv2 headersPatrick Georgi2015-05-2113-13/+13
* Unify byte order macros and clrsetbitsJulius Werner2015-04-212-76/+2
* arch/mips: simplify cache operationsIonela Voinescu2015-04-212-4/+7
* mips: Allow memory to be identity mapped in the TLBAndrew Bresticker2015-04-212-0/+132
* arch/mips: Fix bug when performing cache operationsIonela Voinescu2015-04-171-1/+1
* arch/mips: provide proper cache primitivesIonela Voinescu2015-04-131-0/+29
* urara: add support for DMA coherent memory areaIonela Voinescu2015-04-131-1/+1
* mips: add c0 register access plumbingVadim Bendebury2015-04-071-0/+48
* New mechanism to define SRAM/memory map with automatic bounds checkingJulius Werner2015-04-062-0/+63
* mips: bring payload execution to current standardsPatrick Georgi2015-03-301-1/+0
* mips: fix API expectations that break buildsAaron Durbin2015-03-281-1/+2
* arch/mips: Add base MIPS architecture supportPaul Burton2015-03-2110-0/+449