Commit message (Expand) | Author | Age | Files | Lines | |
---|---|---|---|---|---|
* | Remove address from GPLv2 headers | Patrick Georgi | 2015-05-21 | 15 | -15/+15 |
* | Unify byte order macros and clrsetbits | Julius Werner | 2015-04-21 | 2 | -76/+2 |
* | arch/mips: simplify cache operations | Ionela Voinescu | 2015-04-21 | 2 | -4/+7 |
* | mips: Allow memory to be identity mapped in the TLB | Andrew Bresticker | 2015-04-21 | 2 | -0/+132 |
* | arch/mips: Fix bug when performing cache operations | Ionela Voinescu | 2015-04-17 | 1 | -1/+1 |
* | arch/mips: provide proper cache primitives | Ionela Voinescu | 2015-04-13 | 1 | -0/+29 |
* | urara: add support for DMA coherent memory area | Ionela Voinescu | 2015-04-13 | 1 | -1/+1 |
* | mips: add c0 register access plumbing | Vadim Bendebury | 2015-04-07 | 1 | -0/+48 |
* | New mechanism to define SRAM/memory map with automatic bounds checking | Julius Werner | 2015-04-06 | 2 | -0/+63 |
* | mips: bring payload execution to current standards | Patrick Georgi | 2015-03-30 | 1 | -1/+0 |
* | mips: fix API expectations that break builds | Aaron Durbin | 2015-03-28 | 2 | -1/+7 |
* | arch/mips: Add base MIPS architecture support | Paul Burton | 2015-03-21 | 12 | -0/+578 |