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* spi_flash: document expected return valuesAaron Durbin2015-05-151-0/+1
| | | | | | | | | | | | | | The spi_flash API did not have any of its callbacks documented. Do that so that people don't have to go into the guts of an implementation to figure out the proper expectations. Change-Id: I55a0515445cab3697813d88373ee413f30b557b5 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/10206 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* console: Bring back newline translationKyösti Mälkki2015-05-151-0/+8
| | | | | | | | Change-Id: Ib42f4a9eeb48dfb1a04e332aeb8f83dc4c4eef91 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/10188 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* superio: Replace the indexed I/O functionsDave Frodin2015-05-147-59/+39
| | | | | | | | | | | Replace the multiple indexed I/O read and write functions with common functions. Change-Id: Idfe7a8784c28d51b3fbcb2f4e26beaa0b91741a8 Signed-off-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-on: http://review.coreboot.org/10145 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
* bd82x6x, ibexpeak: Support fully locking ROM on S3 resume.Vladimir Serbinenko2015-05-142-9/+33
| | | | | | | | | | Currently only RO-lock is supported. Make full lock available as an option. Change-Id: Ib68a1e82733a51053a9adc80ac501b6205c6b8a7 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/10191 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
* regions: add mmap helper deviceAaron Durbin2015-05-142-0/+55
| | | | | | | | | | | | In order to facilitate platforms which need a buffer cache for performing boot device operations provide infrastructure to share the logic in managing the buffer and operations. Change-Id: I45dd9f213029706ff92a3e5a2c9edd5e8b541e27 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9132 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* regions: add memory region device supportAaron Durbin2015-05-142-0/+61
| | | | | | | | | | | Provide common code for using memory-backed region devices. This allows in-memory buffers to act as a region device. Change-Id: I266cd07bbfa16a427c2b31c512e7c87b77f47718 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9131 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* coreboot: add memory pool infrastructureAaron Durbin2015-05-143-0/+129
| | | | | | | | | | | | | | The memory pool infrastructure provides an allocator with very simple free()ing semantics: only the most recent allocation can be freed from the pool. However, it can be reset and when not used any longer providing the entire region for future allocations. Change-Id: I5ae9ab35bb769d78bbc2866c5ae3b5ce2cdce5fa Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9129 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* coreboot: add region infrastructureAaron Durbin2015-05-143-0/+225
| | | | | | | | | | | | | | | | The region infrastructure provides a means of abstracting access to different types of storage such as SPI flash, MMC, or just plain memory. The regions are represented by region devices which can be chained together forming subregions of the larger region. This allows the call sites to be agnostic about the implementations behind the regions. Additionally, this prepares for a cleaner API for CBFS accesses. Change-Id: I803f97567ef0505691a69975c282fde1215ea6da Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9128 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* superio/nct5104d: Handle shared GPIO/UART pinsKyösti Mälkki2015-05-141-0/+37
| | | | | | | | | | | | | Routing is decided based on enabled logical/virtual devices. For a valid devicetree, one should have only one of SP3 and GPIO0, and only one of SP4 and GPIO1, enabled at a time in configuration. Change-Id: I02017786aba9dd22d12403aaa71d7641f5bbf997 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/10177 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
* superio/nct5104d: Refactor IRQ trigger configKyösti Mälkki2015-05-141-11/+27
| | | | | | | | | | | | That function was getting too long. Change-Id: Ic50f210391c2467b65215aa556269b0ba601c2ec Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/10176 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
* lenovo: Disable radio when suspending or turning off.Vladimir Serbinenko2015-05-1411-6/+21
| | | | | | | | | | | | Without this some radios may remain operational. They may consume power but the immediate demonstrable effect is wireless LED still being on. Coreboot will reenable radios on resume or poweron. Change-Id: I9fcb08880964b1594f779a246840bc3013a44afe Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/10190 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
* x230: Fix VGA PCIIDs.Vladimir Serbinenko2015-05-141-1/+5
| | | | | | | | | | x230 is ivy, not sandy. Fix copy-paste error. Change-Id: Ic462bab39ddac0e1e6fef1e043970957e45fb6ed Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/10189 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
* 3rdparty/blobs: Move submodule marker forwardMarc Jones2015-05-131-0/+0
| | | | | | | | | | | | | Move the 3rdparty/blobs marker to include the following: a710941 amd/pi: Move AGESA cbfs access function to coreboot 63f1db5 AMD avalon: add PSP firmwares Change-Id: Ie12b273ab9d22ab440b477919e70419b21cb833b Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/10202 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
* vboot: fix die() hang for recovery pathAaron Durbin2015-05-131-0/+4
| | | | | | | | | | | | When we are taking the recovery path there is no slot or components to fill out. Change-Id: Ic97a247629365ef54a340c4398cb7491935edc11 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/10198 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
* amd/pi: Move AGESA cbfs access into the wrapperMarc Jones2015-05-134-0/+33
| | | | | | | | | | | | | The AGESA.c file in 3rdparty has cbfs access functions for locating the AGESA binaries. coreboot access functions need to be within coreboot where they can be updated with cbfs changes. Move the offending function to coreboot. Change-Id: Ibf6136d04dfbdb0198e90cc3ce719dc286c5610e Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/10058 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* cbfstool: Don't typedef the comp_algo enumSol Boucher2015-05-136-18/+18
| | | | | | | | | | | | | | | | | | Our style discourages unnecessary typedefs, and this one doesn't gain us anything, nor is it consistent with the surrounding code: there's a function pointer typedef'd nearby, but non-opaque structs aren't. BUG=chromium:482652 TEST=None BRANCH=None Change-Id: Ie7565240639e5b1aeebb08ea005099aaa3557a27 Signed-off-by: Sol Boucher <solb@chromium.org> Original-Change-Id: I4285e6b56f99b85b9684f2b98b35e9b35a6c4cb7 Original-Signed-off-by: Sol Boucher <solb@chromium.org> Reviewed-on: http://review.coreboot.org/10146 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* cbfstool: Support top-aligned addresses for new-format imagesSol Boucher2015-05-136-26/+52
| | | | | | | | | | | | | | | | | | The cbfstool handling of new-style FMAP-driven "partitioned" images originally disallowed the use of x86-style top-aligned addresses with the add.* and layout actions because it wasn't obvious how they should work, especially since the normal addressing is done relative to each individual region for these types of images. Not surprisingly, however, the x86 portions of the build system make copious use of top-aligned addresses, so this allows their use with new images and specifies their behavior as being relative to the *image* end---not the region end---just as it is for legacy images. Change-Id: Icecc843f4f8b6bb52aa0ea16df771faa278228d2 Signed-off-by: Sol Boucher <solb@chromium.org> Reviewed-on: http://review.coreboot.org/10136 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* cbfstool: New image format w/ required FMAP and w/o CBFS master headerSol Boucher2015-05-135-154/+563
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | These new-style firmware images use the FMAP of the root of knowledge about their layout, which allows them to have sections containing raw data whose offset and size can easily be determined at runtime or when modifying or flashing the image. Furthermore, they can even have multiple CBFSes, each of which occupies a different FMAP region. It is assumed that the first entry of each CBFS, including the primary one, will be located right at the start of its region. This means that the bootblock needs to be moved into its own FMAP region, but makes the CBFS master header obsolete because, with the exception of the version and alignment, all its fields are redundant once its CBFS has an entry in the FMAP. The version code will be addressed in a future commit before the new format comes into use, while the alignment will just be defined to 64 bytes in both cbfstool and coreboot itself, since there's almost no reason to ever change it in practice. The version code field and all necessary coreboot changes will come separately. BUG=chromium:470407 TEST=Build panther and nyan_big coreboot.rom and image.bin images with and without this patch, diff their hexdumps, and note that no locations differ except for those that do between subsequent builds of the same codebase. Try working with new-style images: use fmaptool to produce an FMAP section from an fmd file having raw sections and multiple CBFSes, pass the resulting file to cbfstool create -M -F, then try printing its layout and CBFSes' contents, add and remove CBFS files, and read and write raw sections. BRANCH=None Change-Id: I7dd2578d2143d0cedd652fdba5b22221fcc2184a Signed-off-by: Sol Boucher <solb@chromium.org> Original-Commit-Id: 8a670322297f83135b929a5b20ff2bd0e7d2abd3 Original-Change-Id: Ib86fb50edc66632f4e6f717909bbe4efb6c874e5 Original-Signed-off-by: Sol Boucher <solb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/265863 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/10135 Tested-by: build bot (Jenkins)
* secmon: allow for serial consoleAaron Durbin2015-05-132-1/+2
| | | | | | | | | | Add necessary checks and objects for secmon serial console. Change-Id: Ibafa19061255ef6847a424922565a866328ff34c Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/10197 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
* verstage: provide support for serial consoleAaron Durbin2015-05-135-2/+7
| | | | | | | | | | | | verstage previously lacked serial console support. Add the necessary objects and macro checks to allow verstage to include the serial console. Change-Id: Ibe911ad347cac0b089f5bc0d4263956f44f3d116 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/10196 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
* vboot: indicate verstage loading on consoleAaron Durbin2015-05-131-0/+2
| | | | | | | | | | | There was no indication of verstage being loaded. Provide this output so that one can follow the flow from console messages. Change-Id: I67ae6bb334608fe10a4a12fe690498afaf6b8366 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/10195 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* console: enumerate all known stagesAaron Durbin2015-05-131-3/+10
| | | | | | | | | | | | There are more stages than currently handled in the initial message from console_init(). Add support for those including an UNKNOWN catchall. Change-Id: I2374db590072bdca8ff35116e2ecb2ad6459b697 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/10194 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* Include back the 306ax microcode again.Vladimir Serbinenko2015-05-131-0/+1
| | | | | | | | | | | | | In ee89435798022021026f511deddf0e3b401ad031 microcode for 306ax was forgotten in migration. Without microcode update my machine experiences random hangs and various misbehaviour. Change-Id: I61c704d88a8a0ed74a16fb3f80cce08e8515e6e2 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/10180 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
* cbmem: Add initial allocation supportLee Leahy2015-05-132-9/+38
| | | | | | | | | | | | | | | Add support to allocate a region just below CBMEM root. This region is reserved for FSP 1.1 to use for its stack and variables. BRANCH=none BUG=None TEST=Build and run on Braswell Change-Id: I1d4b36ab366e6f8e036335c56c1756f2dfaab3f5 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10148 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* libpayload: x86: correct types used for IOAaron Durbin2015-05-131-4/+4
| | | | | | | | | | | | | | | libpayload on x86 defines u32 and uint32_t as typedefs of unsigned int. However, the readl/writel routines use long. With alias checking this throws type punning errors. Align the readl/writel/inl/outl types with the 32-bit fixed width ones that are exposed. Change-Id: Ie51cff8af4596948f6132e3cb743f1bc4ea8f204 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/10186 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
* x86: expose tsc's timer_monotonic_get() in SMMAaron Durbin2015-05-131-1/+1
| | | | | | | | | | | | | The implementation of timer_monotonic_get() for the tsc module was being guarded from SMM. Allow this to be linked into SMM as the generic spi flash driver now needs this support which can be included in SMM. Change-Id: I3909edecac8de117922c4ea6c53e6e561f6f435b Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/10187 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
* baytrail: broadwell: correct refcode loadingAaron Durbin2015-05-132-2/+2
| | | | | | | | | | | | I messed up the conditionals on loading the reference code. The bug used || instead of && causing 2 reference codes to be loaded. Change-Id: I29a046bf0e8dc29a9efdb636ebfd04e11eb73f82 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/10185 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
* vboot: handle RELOCATABLE_RAMSTAGEAaron Durbin2015-05-131-1/+11
| | | | | | | | | | | The support for RELOCATABLE_RAMSTAGE was accidentally omitted in the vboot loader. Add said support. Change-Id: I569918823253c33f698acefd6a619133543c7aef Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/10184 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
* FSP 1.1 Comparison BaseLee Leahy2015-05-128-0/+1422
| | | | | | | | | | | | | | Add FSP 1.0 source for comparison with FSP 1.1. BRANCH=none BUG=None TEST=None Change-Id: I8df349f97acfa74f4de3607d49633da3d4884546 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10116 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* kconfig: properly build parser when LKC_GENPARSER=1Patrick Georgi2015-05-121-2/+6
| | | | | | | | | | The rules didn't actually trigger to rebuild the parser. Change-Id: Id51aaa9816b069204c119622d60f7b728b762cad Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/10168 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* libpayload: Fix passing BAR to EHCI driverPatrick Georgi2015-05-121-2/+2
| | | | | | | | | | | The EHCI driver never looked for the base address handed to it but instead used an uninitialized field for that information. Change-Id: I89fe0cc212092672b36e978083e3de78419b1eb5 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: http://review.coreboot.org/10179 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* usbdebug: Add FTDI FT232H supportKyösti Mälkki2015-05-122-2/+91
| | | | | | | | | | | | | | | | Tested with gizmosphere/gizmo1 Explorer add-on board, which exposes the following device: 0x0403 Future Technology Devices International, Ltd 0x6014 FT232H Single HS USB-UART/FIFO IC For now UART is hard-coded to 115200, 8n1, no flow-control. Change-Id: I4081f84f7700751ccbf079e7fcbb1467aa71d872 Signed-off-by: Nico Huber <nico.h@gmx.de> Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/10063 Tested-by: build bot (Jenkins)
* vboot: allow for dynamic work buffersAaron Durbin2015-05-113-2/+24
| | | | | | | | | | | | | | | The vboot library currently relies on link-time known address and sizes of the work buffer. Not all platforms can provide such semantics. Therefore, add an option to use cbmem for the work buffer. This implies such platforms can only do verification of the firmware after main memory has been initialized. Change-Id: If0b0f6b2a187b5c1fb56af08b6cb384a935be096 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/10157 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* vboot: add vb2_working_data_size()Aaron Durbin2015-05-113-2/+10
| | | | | | | | | | | | | | Instead of using the symbols directly provide a size function to provide symmetry between getting the work data and size. It also allows for an abstraction where the linker symbols may not be the only source of this information. Change-Id: I4568064a0050d118c3544ab1ea59a08eb0bad8e4 Signed-off-by: Aaron Durbi <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/10156 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* chromeos: remove vboot_verify_firmware()Aaron Durbin2015-05-114-10/+0
| | | | | | | | | | | | | vboot_verify_firmware() was only defined to ease upstreaming. It was only an empty inline as it is so remove it. Additionally, vboot2 does not require romstage_handoff so there's no need in adding it for the nyan boards. Change-Id: I4d84ac9fb60c756cf10742f26503f7f11af5f57b Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/10155 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* vboot: inject vboot loader for stage loadingAaron Durbin2015-05-1112-188/+280
| | | | | | | | | | | | | | | | | | As previously done the vboot loader can be optionally inserted in the stage loading logic in order to decide the source of each stage. This current patch allows for verstage to be loaded and interrogated for the source of all subsequent stages. Additionally, it's also possible to build this logic directly into one of the additional stages. Note that this patch does not allow x86 to work. Change-Id: Iece018f01b220720c2803dc73c60b2c080d637d0 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/10154 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
* imd: don't recover on limit == 0Aaron Durbin2015-05-111-0/+3
| | | | | | | | | | | | | | | | | | If the limit of the large starting region was set with a NULL pointer then the limit field will be 0. If the limit is zero then no attempt to recover is necessary as there is no region to recover. This prevented an early call cbmem_find() from hanging a rambi device. The config was with vboot enabled and was way before memory init in the sequence. Change-Id: I7163d93c31ecef2c108a6dde0206dc0b6f158b5c Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/10175 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
* vboot2: Use the right set of compiler flags for building vboot librariesPatrick Georgi2015-05-111-1/+2
| | | | | | | | | | | | This make it pass through -fno-stack-protector, and also uses libverstage fields consistently. verstage is for 'stage' stuff, libverstage for all the vboot logic. Change-Id: I3032e072414bed52effd2dc5057896781ad562c6 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: http://review.coreboot.org/10174 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
* vboot: allow options to be selected from .configAaron Durbin2015-05-111-4/+4
| | | | | | | | | | | | In order to allow easier setting of variables without changing mainboards and/or chipset Kconfig files allow the vboot options to be selected by the user. Change-Id: I6e995eb209b4cd63c73ef679d0c5699759d129f5 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/10153 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* vboot: fix vboot_reference compilationAaron Durbin2015-05-111-2/+11
| | | | | | | | | | | | The VB_FIRMWARE_ARCH variable was not being set correctly, and the VBOOT_STARTS_IN_BOOTBLOCK Kconfig option was not properly prefixed with CONFIG_. Correct both of these oversights. Change-Id: Id27974c285d2629bd47b90b6a93aca1ec8a76512 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/10152 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* chromeos: add missing vboot functionsAaron Durbin2015-05-111-2/+17
| | | | | | | | | | | | | | | | Somewhere along the development path the following vboot functions were dropped: int vboot_enable_developer(void) int vboot_enable_recovery(void) Add them back, but also refactor the flag extraction so as not duplicate all that same logic. Change-Id: Id58f3b99f29caeff98b2d3111cfa28241d15b54f Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/10151 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* arm64: update verstage linkingAaron Durbin2015-05-111-2/+3
| | | | | | | | | | | | The linker scripts are added to stage objs so remove those from the object lists. boot.c will be needed to link verstage properly. Change-Id: Ib8427fe015b72e2282219f116a39949739a0af48 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/10150 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* arm: update verstage linkingAaron Durbin2015-05-111-3/+4
| | | | | | | | | | | | The linker scripts are added to stage objs so remove those from the object lists. boot.c will be needed to link verstage properly. Lastly, VERSTAGE_LIB has no value so remove it. Change-Id: Ie53b42c4995a96006463ec5b358aa43a731cb1b8 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/10149 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* cache: Add arch_program_segment_loaded call to arm and arm64Furquan Shaikh2015-05-112-0/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | arch_program_segment_loaded ensures that the program segment loaded is synced back from the cache to PoC. dcache_flush_all on arm64 does not guarantee PoC in case of MP systems. Thus, it is important to track and sync back all the required segments using arch_program_segment_loaded. Use this function in rmodules as well instead of cache_sync_instructions which guarantees sync upto PoC. BUG=chrome-os-partner:37546 BRANCH=None TEST=Boots into depthcharge on foster Change-Id: I64c2dd5e40ea59fa31f300174ca0d0aebcf8041d Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 35ba0b882b86ff2c29ac766e1d65f403c8346247 Original-Change-Id: I964aa09f0cafdaab170606cd4b8f2e027698aee7 Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/260908 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Original-Trybot-Ready: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/10173 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
* secmon: Add some missing filesPatrick Georgi2015-05-112-0/+2
| | | | | | | | | | | secmon is referring to uart's default_baudrate() and various coreboot version strings. Change-Id: I40a8d1979146058409a814d94ea24de83ee4d634 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10129 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* nvidia/tegra132: we write tables in ramstagePatrick Georgi2015-05-111-1/+1
| | | | | | | | | | So that's more precise than "anything non-pre-ram". Change-Id: I21db536a5ea704c4b087f57d0b761dd3fdf43e3e Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10128 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* kconfig: handle globbed files backwardsPatrick Georgi2015-05-112-675/+925
| | | | | | | | | | | | They're essentially collected on a stack before they're parsed. So we push them backwards, then parse them in the correct order. Change-Id: Ibf29559389cd19f260d67bae8e0b5ef9f4f58d91 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/10169 Tested-by: build bot (Jenkins) Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
* AGESA: Drop unused AGESA_MEM_TABLEKyösti Mälkki2015-05-1026-1243/+0
| | | | | | | | | | | | | | These tables are not referenced anywhere, thus all comments about adjustments are void. Also drop stub AgesaReadSpd that is all commented out. Change-Id: I12233ea0dc4baaf36a75f359c52cc59c9b6dad79 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/10143 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com> Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
* cbfstool: fix 32bit host issuePatrick Georgi2015-05-091-1/+1
| | | | | | | | | Change-Id: Iaec748b4bdbb5da287520fbbd7c3794bf664eff6 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/10161 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Sol Boucher <solb@chromium.org>
* fmap: request libc compatibility level that includes memccpyPatrick Georgi2015-05-091-0/+2
| | | | | | | | Change-Id: I928efe6f63305a0099d64e83091aa80768582f48 Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-on: http://review.coreboot.org/10160 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>