aboutsummaryrefslogtreecommitdiffstats
path: root/src/arch
diff options
context:
space:
mode:
Diffstat (limited to 'src/arch')
-rw-r--r--src/arch/arm/Kconfig1
-rw-r--r--src/arch/arm/Makefile.inc2
-rw-r--r--src/arch/arm/armv4/Kconfig11
-rw-r--r--src/arch/arm/armv4/Makefile.inc63
-rw-r--r--src/arch/arm/armv4/bootblock.S98
-rw-r--r--src/arch/arm/armv4/bootblock_simple.c43
-rw-r--r--src/arch/arm/armv4/cache.c81
-rw-r--r--src/arch/arm/include/armv4/arch/arch_io.h58
-rw-r--r--src/arch/arm/include/armv4/arch/cache.h94
9 files changed, 450 insertions, 1 deletions
diff --git a/src/arch/arm/Kconfig b/src/arch/arm/Kconfig
index 050cd62a2..7ec581241 100644
--- a/src/arch/arm/Kconfig
+++ b/src/arch/arm/Kconfig
@@ -11,6 +11,7 @@ config ARCH_RAMSTAGE_ARM
bool
default n
+source src/arch/arm/armv4/Kconfig
source src/arch/arm/armv7/Kconfig
# If a custom bootblock is necessary, this option should be "select"-ed by
diff --git a/src/arch/arm/Makefile.inc b/src/arch/arm/Makefile.inc
index 8838edfd4..09f2fd3f5 100644
--- a/src/arch/arm/Makefile.inc
+++ b/src/arch/arm/Makefile.inc
@@ -23,7 +23,7 @@
###############################################################################
# Take care of subdirectories
###############################################################################
-subdirs-y += armv7/
+subdirs-y += armv4/ armv7/
###############################################################################
# ARM specific options
diff --git a/src/arch/arm/armv4/Kconfig b/src/arch/arm/armv4/Kconfig
new file mode 100644
index 000000000..e40a6e1af
--- /dev/null
+++ b/src/arch/arm/armv4/Kconfig
@@ -0,0 +1,11 @@
+config ARCH_BOOTBLOCK_ARMV4
+ def_bool n
+ select ARCH_BOOTBLOCK_ARM
+
+config ARCH_ROMSTAGE_ARMV4
+ def_bool n
+ select ARCH_ROMSTAGE_ARM
+
+config ARCH_RAMSTAGE_ARMV4
+ def_bool n
+ select ARCH_RAMSTAGE_ARM
diff --git a/src/arch/arm/armv4/Makefile.inc b/src/arch/arm/armv4/Makefile.inc
new file mode 100644
index 000000000..d054b31e4
--- /dev/null
+++ b/src/arch/arm/armv4/Makefile.inc
@@ -0,0 +1,63 @@
+################################################################################
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2013 The ChromiumOS Authors
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+###############################################################################
+
+armv4_flags = -marm -march=armv4t -I$(src)/arch/arm/include/armv4/
+
+###############################################################################
+# bootblock
+###############################################################################
+
+ifeq ($(CONFIG_ARCH_BOOTBLOCK_ARMV4),y)
+
+ifneq ($(CONFIG_ARM_BOOTBLOCK_CUSTOM),y)
+bootblock-y += bootblock.S
+bootblock-y += bootblock_simple.c
+endif
+
+bootblock-y += cache.c
+
+CFLAGS_bootblock += $(armv4_flags)
+CPPFLAGS_bootblock += $(armv4_flags)
+
+endif # CONFIG_ARCH_BOOTBLOCK_ARMV4
+
+###############################################################################
+# romstage
+###############################################################################
+
+ifeq ($(CONFIG_ARCH_ROMSTAGE_ARMV4),y)
+
+
+CFLAGS_romstage += $(armv4_flags)
+CPPFLAGS_romstage += $(armv4_flags)
+
+endif # CONFIG_ARCH_ROMSTAGE_ARMV4
+
+###############################################################################
+# ramstage
+###############################################################################
+
+ifeq ($(CONFIG_ARCH_RAMSTAGE_ARMV4),y)
+
+CFLAGS_ramstage += $(armv4_flags)
+CPPFLAGS_ramstage += $(armv4_flags)
+
+endif # CONFIG_ARCH_RAMSTAGE_ARMV4
diff --git a/src/arch/arm/armv4/bootblock.S b/src/arch/arm/armv4/bootblock.S
new file mode 100644
index 000000000..5f7de13ee
--- /dev/null
+++ b/src/arch/arm/armv4/bootblock.S
@@ -0,0 +1,98 @@
+/*
+ * Early initialization code for ARM architecture.
+ *
+ * This file is based off of the OMAP3530/ARM Cortex start.S file from Das
+ * U-Boot, which itself got the file from armboot.
+ *
+ * Copyright (c) 2004 Texas Instruments <r-woodruff2@ti.com>
+ * Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
+ * Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
+ * Copyright (c) 2002 Gary Jennejohn <garyj@denx.de>
+ * Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com>
+ * Copyright (c) 2003 Kshitij <kshitij@ti.com>
+ * Copyright (c) 2006-2008 Syed Mohammed Khasim <x0khasim@ti.com>
+ * Copyright (c) 2013 The Chromium OS Authors
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+.section ".start", "a", %progbits
+.globl _start
+_start: b reset
+ .balignl 16,0xdeadbeef
+
+_cbfs_master_header:
+ /* The CBFS master header is inserted by cbfstool at the first
+ * aligned offset after the above anchor string is found.
+ * Hence, we leave some space for it.
+ */
+ .skip 128 @ Assumes 64-byte alignment
+
+reset:
+ /*
+ * Set the cpu to System mode with IRQ and FIQ disabled. Prefetch/Data
+ * aborts may happen early and crash before the abort handlers are
+ * installed, but at least the problem will show up near the code that
+ * causes it.
+ */
+ msr cpsr_cxf, #0xdf
+
+ /*
+ * Initialize the stack to a known value. This is used to check for
+ * stack overflow later in the boot process.
+ */
+ ldr r0, .Stack
+ ldr r1, .Stack_size
+ sub r0, r0, r1
+ ldr r1, .Stack
+ ldr r2, =0xdeadbeef
+init_stack_loop:
+ str r2, [r0]
+ add r0, #4
+ cmp r0, r1
+ bne init_stack_loop
+
+/* Set stackpointer in internal RAM to call board_init_f */
+call_bootblock:
+ ldr sp, .Stack /* Set up stack pointer */
+ ldr r0,=0x00000000
+ /*
+ * The current design of cpu_info places the
+ * struct at the top of the stack. The number of
+ * words pushed must be at least as large as that
+ * struct.
+ */
+ push {r0-r2}
+ bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
+ /*
+ * Use "bl" instead of "b" even though we do not intend to return.
+ * "bl" gets compiled to "blx" if we're transitioning from ARM to
+ * Thumb. However, "b" will not and GCC may attempt to create a
+ * wrapper which is currently broken.
+ */
+ bl main
+
+/* we do it this way because it's a 32-bit constant and
+ * in some cases too far away to be loaded as just an offset
+ * from IP
+ */
+.align 2
+.Stack:
+ .word CONFIG_STACK_TOP
+.align 2
+/* create this size the same way we do in coreboot_ram.ld: top-bottom */
+.Stack_size:
+ .word CONFIG_STACK_TOP - CONFIG_STACK_BOTTOM
diff --git a/src/arch/arm/armv4/bootblock_simple.c b/src/arch/arm/armv4/bootblock_simple.c
new file mode 100644
index 000000000..9917dbb5a
--- /dev/null
+++ b/src/arch/arm/armv4/bootblock_simple.c
@@ -0,0 +1,43 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2010 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <arch/hlt.h>
+#include <arch/stages.h>
+#include <bootblock_common.h>
+#include <cbfs.h>
+#include <console/console.h>
+
+void main(void)
+{
+ const char *stage_name = "fallback/romstage";
+ void *entry;
+
+ bootblock_cpu_init();
+ bootblock_mainboard_init();
+
+ if (CONFIG_BOOTBLOCK_CONSOLE)
+ console_init();
+
+ entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, stage_name);
+
+ if (entry) stage_exit(entry);
+ hlt();
+}
diff --git a/src/arch/arm/armv4/cache.c b/src/arch/arm/armv4/cache.c
new file mode 100644
index 000000000..729b82c41
--- /dev/null
+++ b/src/arch/arm/armv4/cache.c
@@ -0,0 +1,81 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2013 Google Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * cache.c: Cache maintenance routines for ARMv7-A and ARMv7-R
+ *
+ * Reference: ARM Architecture Reference Manual, ARMv7-A and ARMv7-R edition
+ */
+
+#include <stdint.h>
+
+#include <arch/cache.h>
+
+void tlb_invalidate_all(void)
+{
+}
+
+void icache_invalidate_all(void)
+{
+}
+
+void dcache_clean_all(void)
+{
+}
+
+void dcache_clean_invalidate_all(void)
+{
+}
+
+void dcache_invalidate_all(void)
+{
+}
+
+void dcache_clean_by_mva(void const *addr, size_t len)
+{
+}
+
+void dcache_clean_invalidate_by_mva(void const *addr, size_t len)
+{
+}
+
+void dcache_invalidate_by_mva(void const *addr, size_t len)
+{
+}
+
+void dcache_mmu_disable(void)
+{
+}
+
+
+void dcache_mmu_enable(void)
+{
+}
+
+void arm_invalidate_caches(void)
+{
+}
diff --git a/src/arch/arm/include/armv4/arch/arch_io.h b/src/arch/arm/include/armv4/arch/arch_io.h
new file mode 100644
index 000000000..72653da3f
--- /dev/null
+++ b/src/arch/arm/include/armv4/arch/arch_io.h
@@ -0,0 +1,58 @@
+/*
+ * Originally imported from linux/include/asm-arm/io.h. This file has changed
+ * substantially since then.
+ *
+ * Copyright 2013 Google Inc.
+ * Copyright (C) 1996-2000 Russell King
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Modifications:
+ * 08-Apr-2013 G Replaced several macros with inlines for type safety.
+ * 16-Sep-1996 RMK Inlined the inx/outx functions & optimised for both
+ * constant addresses and variable addresses.
+ * 04-Dec-1997 RMK Moved a lot of this stuff to the new architecture
+ * specific IO header files.
+ * 27-Mar-1999 PJB Second parameter of memcpy_toio is const..
+ * 04-Apr-1999 PJB Added check_signature.
+ * 12-Dec-1999 RMK More cleanups
+ * 18-Jun-2000 RMK Removed virt_to_* and friends definitions
+ */
+#ifndef __ASM_ARM_ARCH_IO_H
+#define __ASM_ARM_ARCH_IO_H
+
+#include <stdint.h>
+
+static inline uint8_t read8(const void *addr)
+{
+ return *(volatile uint8_t *)addr;
+}
+
+static inline uint16_t read16(const void *addr)
+{
+ return *(volatile uint16_t *)addr;
+}
+
+static inline uint32_t read32(const void *addr)
+{
+ return *(volatile uint32_t *)addr;
+}
+
+static inline void write8(uint8_t val, void *addr)
+{
+ *(volatile uint8_t *)addr = val;
+}
+
+static inline void write16(uint16_t val, void *addr)
+{
+ *(volatile uint16_t *)addr = val;
+}
+
+static inline void write32(uint32_t val, void *addr)
+{
+ *(volatile uint32_t *)addr = val;
+}
+
+#endif /* __ASM_ARM_ARCH_IO_H */
diff --git a/src/arch/arm/include/armv4/arch/cache.h b/src/arch/arm/include/armv4/arch/cache.h
new file mode 100644
index 000000000..db4379a4c
--- /dev/null
+++ b/src/arch/arm/include/armv4/arch/cache.h
@@ -0,0 +1,94 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2013 Google Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * cache.h: Cache maintenance API for ARM
+ */
+
+#ifndef ARM_CACHE_H
+#define ARM_CACHE_H
+
+#include <config.h>
+#include <stddef.h>
+#include <stdint.h>
+
+/*
+ * Cache maintenance API
+ */
+
+/* dcache clean and invalidate all (on current level given by CCSELR) */
+void dcache_clean_invalidate_all(void);
+
+/* dcache clean by modified virtual address to PoC */
+void dcache_clean_by_mva(void const *addr, size_t len);
+
+/* dcache clean and invalidate by modified virtual address to PoC */
+void dcache_clean_invalidate_by_mva(void const *addr, size_t len);
+
+/* dcache invalidate by modified virtual address to PoC */
+void dcache_invalidate_by_mva(void const *addr, size_t len);
+
+void dcache_clean_all(void);
+
+/* dcache invalidate all (on current level given by CCSELR) */
+void dcache_invalidate_all(void);
+
+/* dcache and MMU disable */
+void dcache_mmu_disable(void);
+
+/* dcache and MMU enable */
+void dcache_mmu_enable(void);
+
+/* icache invalidate all (on current level given by CSSELR) */
+void icache_invalidate_all(void);
+
+/* tlb invalidate all */
+void tlb_invalidate_all(void);
+
+/*
+ * Generalized setup/init functions
+ */
+
+/* invalidate all caches on ARM */
+void arm_invalidate_caches(void);
+
+/* mmu initialization (set page table address, set permissions, etc) */
+void mmu_init(void);
+
+enum dcache_policy {
+ DCACHE_OFF,
+ DCACHE_WRITEBACK,
+ DCACHE_WRITETHROUGH,
+};
+
+/* disable the mmu for a range. Primarily useful to lock out address 0. */
+void mmu_disable_range(unsigned long start_mb, unsigned long size_mb);
+/* mmu range configuration (set dcache policy) */
+void mmu_config_range(unsigned long start_mb, unsigned long size_mb,
+ enum dcache_policy policy);
+
+#endif /* ARM_CACHE_H */