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-rw-r--r--src/arch/riscv/Makefile.inc18
-rw-r--r--src/arch/riscv/bootblock.S2
-rw-r--r--src/arch/riscv/include/arch/header.ld (renamed from src/arch/riscv/bootblock.ld)33
-rw-r--r--src/arch/riscv/include/arch/memlayout.h31
-rw-r--r--src/arch/riscv/include/arch/stages.h2
-rw-r--r--src/arch/riscv/ramstage.ld134
-rw-r--r--src/arch/riscv/romstage.ld83
7 files changed, 44 insertions, 259 deletions
diff --git a/src/arch/riscv/Makefile.inc b/src/arch/riscv/Makefile.inc
index 643facff8..7f55e1fa3 100644
--- a/src/arch/riscv/Makefile.inc
+++ b/src/arch/riscv/Makefile.inc
@@ -38,12 +38,10 @@ bootblock-y += \
$(top)/src/lib/memmove.c \
$(top)/src/lib/memset.c
-bootblock-y += bootblock.ld
-
-$(objcbfs)/bootblock.debug: $(obj)/arch/riscv/bootblock.bootblock.ld $$(bootblock-objs)
+$(objcbfs)/bootblock.debug: $$(bootblock-objs)
@printf " LINK $(subst $(obj)/,,$(@))\n"
$(LD_bootblock) --gc-sections -static -o $@ -L$(obj) \
- -T $(obj)/arch/riscv/bootblock.bootblock.ld --start-group $(bootblock-objs) \
+ -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.bootblock.ld --start-group $(filter-out %.ld,$(bootblock-objs)) \
$(LIBGCC_FILE_NAME_bootblock) --end-group
endif
@@ -65,13 +63,11 @@ romstage-y += \
romstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c
-romstage-y += romstage.ld
-
# Build the romstage
-$(objcbfs)/romstage.debug: $$(romstage-objs) $(obj)/arch/riscv/romstage.romstage.ld
+$(objcbfs)/romstage.debug: $$(romstage-objs)
@printf " LINK $(subst $(obj)/,,$(@))\n"
- $(LD_romstage) --gc-sections -static -o $@ -L$(obj) -T $(obj)/arch/riscv/romstage.romstage.ld --start-group $(romstage-objs) --end-group
+ $(LD_romstage) --gc-sections -static -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.romstage.ld --start-group $(filter-out %.ld,$(romstage-objs)) --end-group
romstage-c-ccopts += $(riscv_flags)
romstage-S-ccopts += $(riscv_asm_flags)
@@ -103,15 +99,13 @@ $(eval $(call create_class_compiler,rmodules,riscv))
ramstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c
-ramstage-y += ramstage.ld
-
ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/mainboard.c
# Build the ramstage
-$(objcbfs)/ramstage.debug: $$(ramstage-objs) $(obj)/arch/riscv/ramstage.ramstage.ld
+$(objcbfs)/ramstage.debug: $$(ramstage-objs)
@printf " CC $(subst $(obj)/,,$(@))\n"
- $(LD_ramstage) --gc-sections -static -o $@ -L$(obj) -T $(obj)/arch/riscv/ramstage.ramstage.ld --start-group $(ramstage-objs) --end-group
+ $(LD_ramstage) --gc-sections -static -o $@ -L$(obj) -T $(obj)/mainboard/$(MAINBOARDDIR)/memlayout.ramstage.ld --start-group $(filter-out %.ld,$(ramstage-objs)) --end-group
ramstage-c-ccopts += $(riscv_flags)
ramstage-S-ccopts += $(riscv_asm_flags)
diff --git a/src/arch/riscv/bootblock.S b/src/arch/riscv/bootblock.S
index 00962c4c1..1461a9cbc 100644
--- a/src/arch/riscv/bootblock.S
+++ b/src/arch/riscv/bootblock.S
@@ -21,7 +21,7 @@
// See LICENSE for license details. relating to the _start code in this file.
#include <arch/encoding.h>
-.section ".start", "ax", %progbits
+.section ".text._start", "ax", %progbits
// Maybe there's a better way.
.space 0x2000
.globl _start
diff --git a/src/arch/riscv/bootblock.ld b/src/arch/riscv/include/arch/header.ld
index e5cb851b3..3c4209990 100644
--- a/src/arch/riscv/bootblock.ld
+++ b/src/arch/riscv/include/arch/header.ld
@@ -1,8 +1,7 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2006 Advanced Micro Devices, Inc.
- * Copyright (C) 2008-2010 coresystems GmbH
+ * Copyright 2014 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -19,7 +18,6 @@
*/
/* We use ELF as output format. So that we can debug the code in some form. */
-OUTPUT_FORMAT("elf64-littleriscv", "elf64-littleriscv", "elf64-littleriscv")
OUTPUT_ARCH(riscv)
PHDRS
@@ -27,30 +25,9 @@ PHDRS
to_load PT_LOAD;
}
+#ifdef __BOOTBLOCK__
ENTRY(_start)
-SECTIONS
-{
- . = CONFIG_BOOTBLOCK_BASE;
-
- .bootblock . : {
- *(.start);
- KEEP(*(.id));
- *(.text);
- *(.text.*);
- *(.rodata);
- *(.rodata.*);
- *(.data);
- *(.data.*);
- *(.bss);
- *(.bss.*);
- *(.sbss);
- *(.sbss.*);
- } : to_load = 0xff
+#else
+ENTRY(stage_entry)
+#endif
- /DISCARD/ : {
- *(.comment)
- *(.note)
- *(.comment.*)
- *(.note.*)
- }
-}
diff --git a/src/arch/riscv/include/arch/memlayout.h b/src/arch/riscv/include/arch/memlayout.h
new file mode 100644
index 000000000..b6f4cba21
--- /dev/null
+++ b/src/arch/riscv/include/arch/memlayout.h
@@ -0,0 +1,31 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* This file contains macro definitions for memlayout.ld linker scripts. */
+
+#ifndef __ARCH_MEMLAYOUT_H
+#define __ARCH_MEMLAYOUT_H
+
+/* TODO: Double-check that that's the correct alignment for our ABI. */
+#define STACK(addr, size) REGION(stack, addr, size, 8)
+
+/* TODO: Need to add DMA_COHERENT region like on ARM? */
+
+#endif /* __ARCH_MEMLAYOUT_H */
+
diff --git a/src/arch/riscv/include/arch/stages.h b/src/arch/riscv/include/arch/stages.h
index 2d1192ae3..3b8543da7 100644
--- a/src/arch/riscv/include/arch/stages.h
+++ b/src/arch/riscv/include/arch/stages.h
@@ -22,7 +22,7 @@
extern void main(void);
-void stage_entry(void) __attribute__((section(".text.stage_entry.riscv")));
+void stage_entry(void) __attribute__((section(".text.stage_entry")));
void stage_exit(void *);
void jmp_to_elf_entry(void *entry, unsigned long buffer, unsigned long size);
diff --git a/src/arch/riscv/ramstage.ld b/src/arch/riscv/ramstage.ld
deleted file mode 100644
index 21c963879..000000000
--- a/src/arch/riscv/ramstage.ld
+++ /dev/null
@@ -1,134 +0,0 @@
-/*
- * Memory map:
- *
- * CONFIG_RAMBASE : text segment
- * : rodata segment
- * : data segment
- * : bss segment
- * : stack
- * : heap
- */
-/*
- * Copyright 2013 Google Inc.
- * Bootstrap code for the STPC Consumer
- * Copyright (c) 1999 by Net Insight AB. All Rights Reserved.
- */
-
-/*
- * Written by Johan Rydberg, based on work by Daniel Kahlin.
- * Rewritten by Eric Biederman
- * 2005.12 yhlu add ramstage cross the vga font buffer handling
- */
-
-ENTRY(stage_entry)
-
-PHDRS
-{
- to_load PT_LOAD;
-}
-
-SECTIONS
-{
- . = 0x100000; /*CONFIG_SYS_SDRAM_BASE;*/
- /* First we place the code and read only data (typically const declared).
- * This could theoretically be placed in rom.
- */
- .text : {
- _text = .;
- _start = .;
- *(.text.stage_entry.riscv);
- *(.text);
- *(.text.*);
- . = ALIGN(16);
- _etext = .;
- } : to_load
-
- .ctors : {
- . = ALIGN(0x100);
- __CTOR_LIST__ = .;
- *(.ctors);
- LONG(0);
- __CTOR_END__ = .;
- }
-
- .rodata : {
- _rodata = .;
- . = ALIGN(4);
- console_drivers = .;
- *(.rodata.console_drivers)
- econsole_drivers = . ;
- . = ALIGN(4);
- pci_drivers = . ;
- *(.rodata.pci_driver)
- epci_drivers = . ;
- cpu_drivers = . ;
- *(.rodata.cpu_driver)
- ecpu_drivers = . ;
- _bs_init_begin = .;
- *(.bs_init)
- LONG(0);
- _bs_init_end = .;
- *(.rodata)
- *(.rodata.*)
- /* kevinh/Ispiri - Added an align, because the objcopy tool
- * incorrectly converts sections that are not long word aligned.
- */
- . = ALIGN(4);
-
- _erodata = .;
- }
- /* After the code we place initialized data (typically initialized
- * global variables). This gets copied into ram by startup code.
- * __data_start and __data_end shows where in ram this should be placed,
- * whereas __data_loadstart and __data_loadend shows where in rom to
- * copy from.
- */
- .data : {
- _data = .;
- *(.data)
- _edata = .;
- }
-
- /* bss does not contain data, it is just a space that should be zero
- * initialized on startup. (typically uninitialized global variables)
- * crt0.S fills between _bss and _ebss with zeroes.
- */
- _bss = .;
- .bss . : {
- *(.bss)
- *(.sbss)
- *(COMMON)
- }
- _ebss = .;
- _end = .;
-
- /* coreboot really "ends" here. Only heap and stack are placed after
- * this line.
- */
-
- _heap = .;
- .heap . : {
- /* Reserve CONFIG_HEAP_SIZE bytes for the heap */
- . = CONFIG_HEAP_SIZE ;
- . = ALIGN(4);
- }
- _eheap = .;
-
- _stack = CONFIG_STACK_BOTTOM;
- _estack = CONFIG_STACK_TOP;
-
- /* The ram segment. This includes all memory used by the memory
- * resident copy of coreboot, except the tables that are produced on
- * the fly, but including stack and heap.
- */
- _ram_seg = _text;
- _eram_seg = _eheap;
-
- /* Discard the sections we don't need/want */
-
- /DISCARD/ : {
- *(.comment)
- *(.note)
- *(.note.*)
- }
-}
diff --git a/src/arch/riscv/romstage.ld b/src/arch/riscv/romstage.ld
deleted file mode 100644
index e49d1c10a..000000000
--- a/src/arch/riscv/romstage.ld
+++ /dev/null
@@ -1,83 +0,0 @@
-/*
- * Memory map:
- *
- * CONFIG_ROMSTAGE_BASE : text segment
- * : rodata segment
- * : data segment
- * : bss segment
- * : stack
- * : heap
- */
-/*
- * Bootstrap code for the STPC Consumer
- * Copyright (c) 1999 by Net Insight AB. All Rights Reserved.
- */
-
-/*
- * Written by Johan Rydberg, based on work by Daniel Kahlin.
- * Rewritten by Eric Biederman
- * 2005.12 yhlu add ramstage cross the vga font buffer handling
- */
-
-/* We use ELF as output format. So that we can debug the code in some form. */
-OUTPUT_FORMAT("elf64-littleriscv", "elf64-littleriscv", "elf64-littleriscv")
-OUTPUT_ARCH(riscv)
-
-PHDRS
-{
- to_load PT_LOAD;
-}
-
-ENTRY(stage_entry)
-
-SECTIONS
-{
- . = CONFIG_ROMSTAGE_BASE;
-
- .romtext . : {
- _start = .;
- *(.text.stage_entry.riscv);
- *(.text.startup);
- *(.text);
- *(.text.*);
- } : to_load
-
- .romdata . : {
- *(.rodata);
- *(.rodata.*);
- *(.machine_param);
- *(.data);
- *(.data.*);
- . = ALIGN(8);
- _erom = .;
- }
-
- __image_copy_end = .;
-
- /* bss does not contain data, it is just a space that should be zero
- * initialized on startup. (typically uninitialized global variables)
- * crt0.S fills between _bss and _ebss with zeroes.
- */
- .bss . : {
- . = ALIGN(8);
- _bss = .;
- *(.bss)
- *(.bss.*)
- *(.sbss)
- *(.sbss.*)
- _ebss = .;
- }
-
- _end = .;
-
- preram_cbmem_console = CONFIG_CONSOLE_PRERAM_BUFFER_BASE;
-
- /* Discard the sections we don't need/want */
- /DISCARD/ : {
- *(.comment)
- *(.note)
- *(.comment.*)
- *(.note.*)
- *(.eh_frame);
- }
-}