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-rw-r--r--src/arch/arm/armv4/cache.c11
-rw-r--r--src/arch/arm/armv7/cache.c15
-rw-r--r--src/arch/arm/include/armv4/arch/cache.h3
-rw-r--r--src/arch/arm/include/armv7/arch/cache.h3
-rw-r--r--src/arch/arm/include/armv7/arch/cpu.h2
5 files changed, 28 insertions, 6 deletions
diff --git a/src/arch/arm/armv4/cache.c b/src/arch/arm/armv4/cache.c
index 729b82c41..e5cf293dc 100644
--- a/src/arch/arm/armv4/cache.c
+++ b/src/arch/arm/armv4/cache.c
@@ -55,6 +55,17 @@ void dcache_invalidate_all(void)
{
}
+unsigned int dcache_line_bytes(void)
+{
+ /*
+ * TODO: Implement this correctly. For now we just return a
+ * reasonable value. It was added during Nyan development and
+ * may be used in bootblock code. It matters only if dcache is
+ * turned on.
+ */
+ return 64;
+}
+
void dcache_clean_by_mva(void const *addr, size_t len)
{
}
diff --git a/src/arch/arm/armv7/cache.c b/src/arch/arm/armv7/cache.c
index acd1f9aef..4ee2687d3 100644
--- a/src/arch/arm/armv7/cache.c
+++ b/src/arch/arm/armv7/cache.c
@@ -194,17 +194,20 @@ void dcache_invalidate_all(void)
dcache_foreach(OP_DCISW);
}
-static unsigned int line_bytes(void)
+unsigned int dcache_line_bytes(void)
{
uint32_t ccsidr;
- unsigned int size;
+ static unsigned int line_bytes = 0;
+
+ if (line_bytes)
+ return line_bytes;
ccsidr = read_ccsidr();
/* [2:0] - Indicates (Log2(number of words in cache line)) - 2 */
- size = 1 << ((ccsidr & 0x7) + 2); /* words per line */
- size *= sizeof(unsigned int); /* bytes per line */
+ line_bytes = 1 << ((ccsidr & 0x7) + 2); /* words per line */
+ line_bytes *= sizeof(unsigned int); /* bytes per line */
- return size;
+ return line_bytes;
}
/*
@@ -217,7 +220,7 @@ static void dcache_op_mva(void const *addr, size_t len, enum dcache_op op)
{
unsigned long line, linesize;
- linesize = line_bytes();
+ linesize = dcache_line_bytes();
line = (uint32_t)addr & ~(linesize - 1);
dsb();
diff --git a/src/arch/arm/include/armv4/arch/cache.h b/src/arch/arm/include/armv4/arch/cache.h
index db4379a4c..6a3f593f2 100644
--- a/src/arch/arm/include/armv4/arch/cache.h
+++ b/src/arch/arm/include/armv4/arch/cache.h
@@ -57,6 +57,9 @@ void dcache_clean_all(void);
/* dcache invalidate all (on current level given by CCSELR) */
void dcache_invalidate_all(void);
+/* returns number of bytes per cache line */
+unsigned int dcache_line_bytes(void);
+
/* dcache and MMU disable */
void dcache_mmu_disable(void);
diff --git a/src/arch/arm/include/armv7/arch/cache.h b/src/arch/arm/include/armv7/arch/cache.h
index ffdb55a70..5210dfe6a 100644
--- a/src/arch/arm/include/armv7/arch/cache.h
+++ b/src/arch/arm/include/armv7/arch/cache.h
@@ -304,6 +304,9 @@ void dcache_clean_all(void);
/* dcache invalidate all (on current level given by CCSELR) */
void dcache_invalidate_all(void);
+/* returns number of bytes per cache line */
+unsigned int dcache_line_bytes(void);
+
/* dcache and MMU disable */
void dcache_mmu_disable(void);
diff --git a/src/arch/arm/include/armv7/arch/cpu.h b/src/arch/arm/include/armv7/arch/cpu.h
index 52cc8a3f5..275bb8c90 100644
--- a/src/arch/arm/include/armv7/arch/cpu.h
+++ b/src/arch/arm/include/armv7/arch/cpu.h
@@ -20,6 +20,8 @@
#ifndef __ARCH_CPU_H__
#define __ARCH_CPU_H__
+#include <stdint.h>
+
#define asmlinkage
#if !defined(__PRE_RAM__)