aboutsummaryrefslogtreecommitdiffstats
path: root/src/arch/arm/include/armv7/arch
diff options
context:
space:
mode:
Diffstat (limited to 'src/arch/arm/include/armv7/arch')
-rw-r--r--src/arch/arm/include/armv7/arch/arch_io.h68
-rw-r--r--src/arch/arm/include/armv7/arch/cache.h341
-rw-r--r--src/arch/arm/include/armv7/arch/cpu.h108
-rw-r--r--src/arch/arm/include/armv7/arch/types.h46
4 files changed, 563 insertions, 0 deletions
diff --git a/src/arch/arm/include/armv7/arch/arch_io.h b/src/arch/arm/include/armv7/arch/arch_io.h
new file mode 100644
index 000000000..360fa6425
--- /dev/null
+++ b/src/arch/arm/include/armv7/arch/arch_io.h
@@ -0,0 +1,68 @@
+/*
+ * Originally imported from linux/include/asm-arm/io.h. This file has changed
+ * substantially since then.
+ *
+ * Copyright 2013 Google Inc.
+ * Copyright (C) 1996-2000 Russell King
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Modifications:
+ * 08-Apr-2013 G Replaced several macros with inlines for type safety.
+ * 16-Sep-1996 RMK Inlined the inx/outx functions & optimised for both
+ * constant addresses and variable addresses.
+ * 04-Dec-1997 RMK Moved a lot of this stuff to the new architecture
+ * specific IO header files.
+ * 27-Mar-1999 PJB Second parameter of memcpy_toio is const..
+ * 04-Apr-1999 PJB Added check_signature.
+ * 12-Dec-1999 RMK More cleanups
+ * 18-Jun-2000 RMK Removed virt_to_* and friends definitions
+ */
+#ifndef __ASM_ARM_ARCH_IO_H
+#define __ASM_ARM_ARCH_IO_H
+
+#include <arch/cache.h> /* for dmb() */
+#include <stdint.h>
+
+static inline uint8_t read8(const void *addr)
+{
+ dmb();
+ return *(volatile uint8_t *)addr;
+}
+
+static inline uint16_t read16(const void *addr)
+{
+ dmb();
+ return *(volatile uint16_t *)addr;
+}
+
+static inline uint32_t read32(const void *addr)
+{
+ dmb();
+ return *(volatile uint32_t *)addr;
+}
+
+static inline void write8(uint8_t val, void *addr)
+{
+ dmb();
+ *(volatile uint8_t *)addr = val;
+ dmb();
+}
+
+static inline void write16(uint16_t val, void *addr)
+{
+ dmb();
+ *(volatile uint16_t *)addr = val;
+ dmb();
+}
+
+static inline void write32(uint32_t val, void *addr)
+{
+ dmb();
+ *(volatile uint32_t *)addr = val;
+ dmb();
+}
+
+#endif /* __ASM_ARM_ARCH_IO_H */
diff --git a/src/arch/arm/include/armv7/arch/cache.h b/src/arch/arm/include/armv7/arch/cache.h
new file mode 100644
index 000000000..ffdb55a70
--- /dev/null
+++ b/src/arch/arm/include/armv7/arch/cache.h
@@ -0,0 +1,341 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2013 Google Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * cache.h: Cache maintenance API for ARM
+ */
+
+#ifndef ARM_CACHE_H
+#define ARM_CACHE_H
+
+#include <stddef.h>
+#include <stdint.h>
+
+/* SCTLR bits */
+#define SCTLR_M (1 << 0) /* MMU enable */
+#define SCTLR_A (1 << 1) /* Alignment check enable */
+#define SCTLR_C (1 << 2) /* Data/unified cache enable */
+/* Bits 4:3 are reserved */
+#define SCTLR_CP15BEN (1 << 5) /* CP15 barrier enable */
+/* Bit 6 is reserved */
+#define SCTLR_B (1 << 7) /* Endianness */
+/* Bits 9:8 */
+#define SCTLR_SW (1 << 10) /* SWP and SWPB enable */
+#define SCTLR_Z (1 << 11) /* Branch prediction enable */
+#define SCTLR_I (1 << 12) /* Instruction cache enable */
+#define SCTLR_V (1 << 13) /* Low/high exception vectors */
+#define SCTLR_RR (1 << 14) /* Round Robin select */
+/* Bits 16:15 are reserved */
+#define SCTLR_HA (1 << 17) /* Hardware Access flag enable */
+/* Bit 18 is reserved */
+/* Bits 20:19 reserved virtualization not supported */
+#define SCTLR_WXN (1 << 19) /* Write permission implies XN */
+#define SCTLR_UWXN (1 << 20) /* Unprivileged write permission
+ implies PL1 XN */
+#define SCTLR_FI (1 << 21) /* Fast interrupt config enable */
+#define SCTLR_U (1 << 22) /* Unaligned access behavior */
+#define SCTLR_VE (1 << 24) /* Interrupt vectors enable */
+#define SCTLR_EE (1 << 25) /* Exception endianness */
+/* Bit 26 is reserved */
+#define SCTLR_NMFI (1 << 27) /* Non-maskable FIQ support */
+#define SCTLR_TRE (1 << 28) /* TEX remap enable */
+#define SCTLR_AFE (1 << 29) /* Access flag enable */
+#define SCTLR_TE (1 << 30) /* Thumb exception enable */
+/* Bit 31 is reserved */
+
+/*
+ * Sync primitives
+ */
+
+/* data memory barrier */
+static inline void dmb(void)
+{
+ asm volatile ("dmb" : : : "memory");
+}
+
+/* data sync barrier */
+static inline void dsb(void)
+{
+ asm volatile ("dsb" : : : "memory");
+}
+
+/* instruction sync barrier */
+static inline void isb(void)
+{
+ asm volatile ("isb" : : : "memory");
+}
+
+/*
+ * Low-level TLB maintenance operations
+ */
+
+/* invalidate entire data TLB */
+static inline void dtlbiall(void)
+{
+ asm volatile ("mcr p15, 0, %0, c8, c6, 0" : : "r" (0) : "memory");
+}
+
+/* invalidate entire instruction TLB */
+static inline void itlbiall(void)
+{
+ asm volatile ("mcr p15, 0, %0, c8, c5, 0" : : "r" (0));
+}
+
+/* invalidate entire unified TLB */
+static inline void tlbiall(void)
+{
+ asm volatile ("mcr p15, 0, %0, c8, c7, 0" : : "r" (0) : "memory");
+}
+
+/* invalidate unified TLB by MVA, all ASID */
+static inline void tlbimvaa(unsigned long mva)
+{
+ asm volatile ("mcr p15, 0, %0, c8, c7, 3" : : "r" (mva) : "memory");
+}
+
+/* write data access control register (DACR) */
+static inline void write_dacr(uint32_t val)
+{
+ asm volatile ("mcr p15, 0, %0, c3, c0, 0" : : "r" (val));
+}
+
+/* write translation table base register 0 (TTBR0) */
+static inline void write_ttbr0(uint32_t val)
+{
+ asm volatile ("mcr p15, 0, %0, c2, c0, 0" : : "r" (val) : "memory");
+}
+
+/* read translation table base control register (TTBCR) */
+static inline uint32_t read_ttbcr(void)
+{
+ uint32_t val = 0;
+ asm volatile ("mrc p15, 0, %0, c2, c0, 2" : "=r" (val));
+ return val;
+}
+
+/* write translation table base control register (TTBCR) */
+static inline void write_ttbcr(uint32_t val)
+{
+ asm volatile ("mcr p15, 0, %0, c2, c0, 2" : : "r" (val) : "memory");
+}
+
+/*
+ * Low-level cache maintenance operations
+ */
+
+/* branch predictor invalidate all */
+static inline void bpiall(void)
+{
+ asm volatile ("mcr p15, 0, %0, c7, c5, 6" : : "r" (0));
+}
+
+/* data cache clean and invalidate by MVA to PoC */
+static inline void dccimvac(unsigned long mva)
+{
+ asm volatile ("mcr p15, 0, %0, c7, c14, 1" : : "r" (mva) : "memory");
+}
+
+/* data cache invalidate by set/way */
+static inline void dccisw(uint32_t val)
+{
+ asm volatile ("mcr p15, 0, %0, c7, c14, 2" : : "r" (val) : "memory");
+}
+
+/* data cache clean by MVA to PoC */
+static inline void dccmvac(unsigned long mva)
+{
+ asm volatile ("mcr p15, 0, %0, c7, c10, 1" : : "r" (mva) : "memory");
+}
+
+/* data cache clean by set/way */
+static inline void dccsw(uint32_t val)
+{
+ asm volatile ("mcr p15, 0, %0, c7, c10, 2" : : "r" (val) : "memory");
+}
+
+/* data cache invalidate by MVA to PoC */
+static inline void dcimvac(unsigned long mva)
+{
+ asm volatile ("mcr p15, 0, %0, c7, c6, 1" : : "r" (mva) : "memory");
+}
+
+/* data cache invalidate by set/way */
+static inline void dcisw(uint32_t val)
+{
+ asm volatile ("mcr p15, 0, %0, c7, c6, 2" : : "r" (val) : "memory");
+}
+
+/* instruction cache invalidate all by PoU */
+static inline void iciallu(void)
+{
+ asm volatile ("mcr p15, 0, %0, c7, c5, 0" : : "r" (0));
+}
+
+/*
+ * Cache co-processor (CP15) access functions
+ */
+
+/* read cache level ID register (CLIDR) */
+static inline uint32_t read_clidr(void)
+{
+ uint32_t val = 0;
+ asm volatile ("mrc p15, 1, %0, c0, c0, 1" : "=r" (val));
+ return val;
+}
+
+/* read cache size ID register register (CCSIDR) */
+static inline uint32_t read_ccsidr(void)
+{
+ uint32_t val = 0;
+ asm volatile ("mrc p15, 1, %0, c0, c0, 0" : "=r" (val));
+ return val;
+}
+
+/* read cache size selection register (CSSELR) */
+static inline uint32_t read_csselr(void)
+{
+ uint32_t val = 0;
+ asm volatile ("mrc p15, 2, %0, c0, c0, 0" : "=r" (val));
+ return val;
+}
+
+/* write to cache size selection register (CSSELR) */
+static inline void write_csselr(uint32_t val)
+{
+ /*
+ * Bits [3:1] - Cache level + 1 (0b000 = L1, 0b110 = L7, 0b111 is rsvd)
+ * Bit 0 - 0 = data or unified cache, 1 = instruction cache
+ */
+ asm volatile ("mcr p15, 2, %0, c0, c0, 0" : : "r" (val));
+ isb(); /* ISB to sync the change to CCSIDR */
+}
+
+/* read L2 control register (L2CTLR) */
+static inline uint32_t read_l2ctlr(void)
+{
+ uint32_t val = 0;
+ asm volatile ("mrc p15, 1, %0, c9, c0, 2" : "=r" (val));
+ return val;
+}
+
+/* write L2 control register (L2CTLR) */
+static inline void write_l2ctlr(uint32_t val)
+{
+ /*
+ * Note: L2CTLR can only be written when the L2 memory system
+ * is idle, ie before the MMU is enabled.
+ */
+ asm volatile("mcr p15, 1, %0, c9, c0, 2" : : "r" (val) : "memory" );
+ isb();
+}
+
+/* read L2 Auxiliary Control Register (L2ACTLR) */
+static inline uint32_t read_l2actlr(void)
+{
+ uint32_t val = 0;
+ asm volatile ("mrc p15, 1, %0, c15, c0, 0" : "=r" (val));
+ return val;
+}
+
+/* write L2 Auxiliary Control Register (L2ACTLR) */
+static inline void write_l2actlr(uint32_t val)
+{
+ asm volatile ("mcr p15, 1, %0, c15, c0, 0" : : "r" (val) : "memory" );
+ isb();
+}
+
+/* read system control register (SCTLR) */
+static inline uint32_t read_sctlr(void)
+{
+ uint32_t val;
+ asm volatile ("mrc p15, 0, %0, c1, c0, 0" : "=r" (val));
+ return val;
+}
+
+/* write system control register (SCTLR) */
+static inline void write_sctlr(uint32_t val)
+{
+ asm volatile ("mcr p15, 0, %0, c1, c0, 0" : : "r" (val) : "cc");
+ isb();
+}
+
+/*
+ * Cache maintenance API
+ */
+
+/* dcache clean and invalidate all (on current level given by CCSELR) */
+void dcache_clean_invalidate_all(void);
+
+/* dcache clean by modified virtual address to PoC */
+void dcache_clean_by_mva(void const *addr, size_t len);
+
+/* dcache clean and invalidate by modified virtual address to PoC */
+void dcache_clean_invalidate_by_mva(void const *addr, size_t len);
+
+/* dcache invalidate by modified virtual address to PoC */
+void dcache_invalidate_by_mva(void const *addr, size_t len);
+
+void dcache_clean_all(void);
+
+/* dcache invalidate all (on current level given by CCSELR) */
+void dcache_invalidate_all(void);
+
+/* dcache and MMU disable */
+void dcache_mmu_disable(void);
+
+/* dcache and MMU enable */
+void dcache_mmu_enable(void);
+
+/* icache invalidate all (on current level given by CSSELR) */
+void icache_invalidate_all(void);
+
+/* tlb invalidate all */
+void tlb_invalidate_all(void);
+
+/*
+ * Generalized setup/init functions
+ */
+
+/* invalidate all caches on ARM */
+void arm_invalidate_caches(void);
+
+/* mmu initialization (set page table address, set permissions, etc) */
+void mmu_init(void);
+
+enum dcache_policy {
+ DCACHE_OFF,
+ DCACHE_WRITEBACK,
+ DCACHE_WRITETHROUGH,
+};
+
+/* disable the mmu for a range. Primarily useful to lock out address 0. */
+void mmu_disable_range(unsigned long start_mb, unsigned long size_mb);
+/* mmu range configuration (set dcache policy) */
+void mmu_config_range(unsigned long start_mb, unsigned long size_mb,
+ enum dcache_policy policy);
+
+#endif /* ARM_CACHE_H */
diff --git a/src/arch/arm/include/armv7/arch/cpu.h b/src/arch/arm/include/armv7/arch/cpu.h
new file mode 100644
index 000000000..52cc8a3f5
--- /dev/null
+++ b/src/arch/arm/include/armv7/arch/cpu.h
@@ -0,0 +1,108 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2012 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA
+ */
+
+#ifndef __ARCH_CPU_H__
+#define __ARCH_CPU_H__
+
+#define asmlinkage
+
+#if !defined(__PRE_RAM__)
+#include <device/device.h>
+
+struct cpu_driver {
+ struct device_operations *ops;
+ struct cpu_device_id *id_table;
+};
+
+struct thread;
+
+struct cpu_info {
+ device_t cpu;
+ unsigned long index;
+#if CONFIG_COOP_MULTITASKING
+ struct thread *thread;
+#endif
+};
+
+struct cpuinfo_arm {
+ uint8_t arm; /* CPU family */
+ uint8_t arm_vendor; /* CPU vendor */
+ uint8_t arm_model;
+};
+
+#endif
+
+/* Primitives for CPU and MP cores. */
+
+/* read Main Id register (MIDR) */
+inline static uint32_t read_midr(void)
+{
+ uint32_t value;
+ asm volatile ("mrc p15, 0, %0, c0, c0, 0" : "=r"(value));
+ return value;
+}
+
+/* read Multiprocessor Affinity Register (MPIDR) */
+inline static uint32_t read_mpidr(void)
+{
+ uint32_t value;
+ asm volatile ("mrc p15, 0, %0, c0, c0, 5" : "=r"(value));
+ return value;
+}
+
+/* read Auxiliary Control Register (ACTLR) */
+inline static uint32_t read_actlr(void)
+{
+ uint32_t val = 0;
+ asm volatile ("mrc p15, 0, %0, c1, c0, 1" : "=r"(val));
+ return val;
+}
+
+/* write Auxiliary Control Register (ACTLR) */
+inline static void write_actlr(uint32_t val)
+{
+ asm volatile ("mcr p15, 0, %0, c1, c0, 1" : : "r" (val));
+}
+
+/* wait for interrupt. */
+inline static void wfi(void)
+{
+ asm volatile ("wfi" : : : "memory");
+}
+
+/* wait for event. */
+inline static void wfe(void)
+{
+ asm volatile ("wfe");
+}
+
+/* set event (to bring up cores in WFE state). */
+inline static void sev(void)
+{
+ asm volatile ("sev");
+}
+
+/* puts CPU into System mode and disable interrupts. */
+inline static void set_system_mode(void)
+{
+ asm volatile("msr cpsr_c, %0" :: "r"(0x1f | 0xc0));
+}
+
+struct cpu_info *cpu_info(void);
+#endif /* __ARCH_CPU_H__ */
diff --git a/src/arch/arm/include/armv7/arch/types.h b/src/arch/arm/include/armv7/arch/types.h
new file mode 100644
index 000000000..be7e76c5a
--- /dev/null
+++ b/src/arch/arm/include/armv7/arch/types.h
@@ -0,0 +1,46 @@
+#ifndef __ASM_ARM_TYPES_H
+#define __ASM_ARM_TYPES_H
+
+typedef unsigned short umode_t;
+
+/*
+ * __xx is ok: it doesn't pollute the POSIX namespace. Use these in the
+ * header files exported to user space
+ */
+
+typedef __signed__ char __s8;
+typedef unsigned char __u8;
+
+typedef __signed__ short __s16;
+typedef unsigned short __u16;
+
+typedef __signed__ int __s32;
+typedef unsigned int __u32;
+
+#if defined(__GNUC__)
+__extension__ typedef __signed__ long long __s64;
+__extension__ typedef unsigned long long __u64;
+#endif
+
+typedef signed char s8;
+typedef unsigned char u8;
+
+typedef signed short s16;
+typedef unsigned short u16;
+
+typedef signed int s32;
+typedef unsigned int u32;
+
+typedef signed long long s64;
+typedef unsigned long long u64;
+
+#define BITS_PER_LONG 32
+
+/* Dma addresses are 32-bits wide. */
+
+typedef u32 dma_addr_t;
+
+typedef unsigned long phys_addr_t;
+typedef unsigned long phys_size_t;
+
+#endif