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-rw-r--r--.gitmodules2
-rw-r--r--Makefile.inc4
m---------blobs (renamed from 3rdparty)0
-rw-r--r--src/cpu/amd/geode_gx2/Makefile.inc2
-rw-r--r--src/cpu/amd/geode_lx/Kconfig2
-rw-r--r--src/cpu/amd/geode_lx/Makefile.inc2
-rw-r--r--src/cpu/intel/haswell/microcode_blob.c4
-rw-r--r--src/cpu/intel/model_1067x/microcode_blob.c2
-rw-r--r--src/cpu/intel/model_106cx/microcode_blob.c2
-rw-r--r--src/cpu/intel/model_2065x/microcode_blob.c2
-rw-r--r--src/cpu/intel/model_206ax/microcode_blob.c2
-rw-r--r--src/cpu/intel/model_65x/microcode_blob.c2
-rw-r--r--src/cpu/intel/model_67x/microcode_blob.c2
-rw-r--r--src/cpu/intel/model_68x/microcode_blob.c2
-rw-r--r--src/cpu/intel/model_69x/microcode_blob.c2
-rw-r--r--src/cpu/intel/model_6bx/microcode_blob.c2
-rw-r--r--src/cpu/intel/model_6dx/microcode_blob.c2
-rw-r--r--src/cpu/intel/model_6ex/microcode_blob.c2
-rw-r--r--src/cpu/intel/model_6fx/microcode_blob.c2
-rw-r--r--src/cpu/intel/model_6xx/microcode_blob.c2
-rw-r--r--src/cpu/intel/model_f0x/microcode_blob.c2
-rw-r--r--src/cpu/intel/model_f1x/microcode_blob.c2
-rw-r--r--src/cpu/intel/model_f2x/microcode_blob.c2
-rw-r--r--src/cpu/intel/model_f3x/microcode_blob.c2
-rw-r--r--src/cpu/intel/model_f4x/microcode_blob.c2
-rw-r--r--src/cpu/samsung/exynos5250/update-bl1.sh2
-rw-r--r--src/mainboard/amd/lamar/Kconfig2
-rw-r--r--src/northbridge/amd/pi/00630F01/Kconfig2
-rw-r--r--src/northbridge/amd/pi/00730F01/Kconfig2
-rw-r--r--src/northbridge/intel/sandybridge/Kconfig2
-rw-r--r--src/soc/intel/baytrail/Kconfig8
-rw-r--r--src/soc/intel/baytrail/microcode/microcode_blob.c2
-rw-r--r--src/soc/intel/broadwell/Kconfig6
-rw-r--r--src/soc/intel/broadwell/microcode/microcode_blob.c2
-rw-r--r--src/soc/nvidia/tegra132/Kconfig2
-rw-r--r--src/soc/qualcomm/ipq806x/Kconfig2
-rw-r--r--src/soc/qualcomm/ipq806x/Makefile.inc2
-rw-r--r--src/soc/samsung/exynos5250/Makefile.inc2
-rw-r--r--src/soc/samsung/exynos5420/Makefile.inc2
-rw-r--r--src/southbridge/amd/agesa/hudson/Kconfig12
-rw-r--r--src/southbridge/amd/agesa/hudson/Makefile.inc4
-rw-r--r--src/southbridge/amd/cimx/sb800/Kconfig2
-rw-r--r--src/southbridge/amd/pi/hudson/Kconfig6
-rw-r--r--src/southbridge/amd/pi/hudson/Makefile.inc4
-rw-r--r--src/southbridge/intel/bd82x6x/Kconfig8
-rw-r--r--src/southbridge/intel/ibexpeak/Kconfig6
-rw-r--r--src/southbridge/intel/lynxpoint/Kconfig6
-rw-r--r--src/vendorcode/amd/Kconfig2
-rw-r--r--src/vendorcode/amd/pi/00630F01/Kconfig2
-rw-r--r--src/vendorcode/amd/pi/00730F01/Kconfig2
-rwxr-xr-xsrc/vendorcode/google/chromeos/build-snow2
51 files changed, 73 insertions, 73 deletions
diff --git a/.gitmodules b/.gitmodules
index ee3f1ea9e..9508b5a62 100644
--- a/.gitmodules
+++ b/.gitmodules
@@ -1,5 +1,5 @@
[submodule "3rdparty"]
- path = 3rdparty
+ path = blobs
url = ../blobs.git
update = none
ignore = dirty
diff --git a/Makefile.inc b/Makefile.inc
index 64039771f..726331568 100644
--- a/Makefile.inc
+++ b/Makefile.inc
@@ -131,9 +131,9 @@ endif
# try to fetch non-optional submodules if the source is under git
forgetthis:=$(if $(GIT),$(shell git submodule update --init))
ifeq ($(CONFIG_USE_BLOBS),y)
-# this is necessary because 3rdparty is update=none, and so is ignored
+# this is necessary because blobs is update=none, and so is ignored
# unless explicitly requested and enabled through --checkout
-forgetthis:=$(if $(GIT),$(shell git submodule update --init --checkout 3rdparty))
+forgetthis:=$(if $(GIT),$(shell git submodule update --init --checkout blobs))
endif
ramstage-c-deps:=$$(OPTION_TABLE_H)
diff --git a/3rdparty b/blobs
-Subproject 892a6976ba8c7d14e1aaa518d4d02923d51b22c
+Subproject 892a6976ba8c7d14e1aaa518d4d02923d51b22c
diff --git a/src/cpu/amd/geode_gx2/Makefile.inc b/src/cpu/amd/geode_gx2/Makefile.inc
index 751192619..074aeda16 100644
--- a/src/cpu/amd/geode_gx2/Makefile.inc
+++ b/src/cpu/amd/geode_gx2/Makefile.inc
@@ -11,4 +11,4 @@ cpu_incs += $(src)/cpu/amd/geode_gx2/cache_as_ram.inc
cbfs-files-$(CONFIG_GEODE_VSA_FILE) += vsa
vsa-file = $(call strip_quotes,$(CONFIG_VSA_FILENAME)):vsa
vsa-type = stage
-vsa-required = VSA binary (binary and MASM source code available in coreboot/3rdparty repository)
+vsa-required = VSA binary (binary and MASM source code available in coreboot/blobs repository)
diff --git a/src/cpu/amd/geode_lx/Kconfig b/src/cpu/amd/geode_lx/Kconfig
index e3e2d2e1c..6d1fd0fc4 100644
--- a/src/cpu/amd/geode_lx/Kconfig
+++ b/src/cpu/amd/geode_lx/Kconfig
@@ -37,7 +37,7 @@ config GEODE_VSA_FILE
config VSA_FILENAME
string "AMD Geode LX VSA path and filename"
depends on GEODE_VSA_FILE
- default "3rdparty/cpu/amd/geode_lx/gpl_vsa_lx_102.bin"
+ default "blobs/cpu/amd/geode_lx/gpl_vsa_lx_102.bin"
help
The path and filename of the file to use as VSA.
diff --git a/src/cpu/amd/geode_lx/Makefile.inc b/src/cpu/amd/geode_lx/Makefile.inc
index 4eb57bad3..ffa0688d6 100644
--- a/src/cpu/amd/geode_lx/Makefile.inc
+++ b/src/cpu/amd/geode_lx/Makefile.inc
@@ -11,4 +11,4 @@ cpu_incs += $(src)/cpu/amd/geode_lx/cache_as_ram.inc
cbfs-files-$(CONFIG_GEODE_VSA_FILE) += vsa
vsa-file = $(call strip_quotes,$(CONFIG_VSA_FILENAME)):vsa
vsa-type = stage
-vsa-required = VSA binary (binary and MASM source code available in coreboot/3rdparty repository)
+vsa-required = VSA binary (binary and MASM source code available in coreboot/blobs repository)
diff --git a/src/cpu/intel/haswell/microcode_blob.c b/src/cpu/intel/haswell/microcode_blob.c
index df54ddbe8..3338cc49b 100644
--- a/src/cpu/intel/haswell/microcode_blob.c
+++ b/src/cpu/intel/haswell/microcode_blob.c
@@ -23,8 +23,8 @@ unsigned microcode[] = {
* a very good reason why we only use one at a time?
*/
#if CONFIG_INTEL_LYNXPOINT_LP
- #include "../../../../3rdparty/cpu/intel/model_4065x/microcode.h"
+ #include "../../../../blobs/cpu/intel/model_4065x/microcode.h"
#else
- #include "../../../../3rdparty/cpu/intel/model_306cx/microcode.h"
+ #include "../../../../blobs/cpu/intel/model_306cx/microcode.h"
#endif
};
diff --git a/src/cpu/intel/model_1067x/microcode_blob.c b/src/cpu/intel/model_1067x/microcode_blob.c
index 36f4caf03..c98d5ff29 100644
--- a/src/cpu/intel/model_1067x/microcode_blob.c
+++ b/src/cpu/intel/model_1067x/microcode_blob.c
@@ -1,3 +1,3 @@
unsigned microcode_updates_1067ax[] = {
- #include "../../../../3rdparty/cpu/intel/model_1067x/microcode.h"
+ #include "../../../../blobs/cpu/intel/model_1067x/microcode.h"
};
diff --git a/src/cpu/intel/model_106cx/microcode_blob.c b/src/cpu/intel/model_106cx/microcode_blob.c
index 97d36edff..94ea96d18 100644
--- a/src/cpu/intel/model_106cx/microcode_blob.c
+++ b/src/cpu/intel/model_106cx/microcode_blob.c
@@ -1,3 +1,3 @@
unsigned microcode_updates_106cx[] = {
- #include "../../../../3rdparty/cpu/intel/model_106cx/microcode.h"
+ #include "../../../../blobs/cpu/intel/model_106cx/microcode.h"
};
diff --git a/src/cpu/intel/model_2065x/microcode_blob.c b/src/cpu/intel/model_2065x/microcode_blob.c
index df2e85b26..35c5c9895 100644
--- a/src/cpu/intel/model_2065x/microcode_blob.c
+++ b/src/cpu/intel/model_2065x/microcode_blob.c
@@ -18,5 +18,5 @@
*/
unsigned microcode[] = {
- #include "../../../../3rdparty/cpu/intel/model_2065x/microcode.h"
+ #include "../../../../blobs/cpu/intel/model_2065x/microcode.h"
};
diff --git a/src/cpu/intel/model_206ax/microcode_blob.c b/src/cpu/intel/model_206ax/microcode_blob.c
index 197daf2bf..dc1c2bd50 100644
--- a/src/cpu/intel/model_206ax/microcode_blob.c
+++ b/src/cpu/intel/model_206ax/microcode_blob.c
@@ -18,5 +18,5 @@
*/
unsigned microcode[] = {
- #include "../../../../3rdparty/cpu/intel/model_206ax/microcode.h"
+ #include "../../../../blobs/cpu/intel/model_206ax/microcode.h"
};
diff --git a/src/cpu/intel/model_65x/microcode_blob.c b/src/cpu/intel/model_65x/microcode_blob.c
index d0f6a2a8e..fcddd617b 100644
--- a/src/cpu/intel/model_65x/microcode_blob.c
+++ b/src/cpu/intel/model_65x/microcode_blob.c
@@ -1,3 +1,3 @@
unsigned microcode_updates_65x[] = {
- #include "../../../../3rdparty/cpu/intel/model_65x/microcode.h"
+ #include "../../../../blobs/cpu/intel/model_65x/microcode.h"
};
diff --git a/src/cpu/intel/model_67x/microcode_blob.c b/src/cpu/intel/model_67x/microcode_blob.c
index 130292834..5c0745620 100644
--- a/src/cpu/intel/model_67x/microcode_blob.c
+++ b/src/cpu/intel/model_67x/microcode_blob.c
@@ -1,3 +1,3 @@
unsigned microcode_updates_67x[] = {
- #include "../../../../3rdparty/cpu/intel/model_67x/microcode.h"
+ #include "../../../../blobs/cpu/intel/model_67x/microcode.h"
};
diff --git a/src/cpu/intel/model_68x/microcode_blob.c b/src/cpu/intel/model_68x/microcode_blob.c
index fa7208630..7246527b2 100644
--- a/src/cpu/intel/model_68x/microcode_blob.c
+++ b/src/cpu/intel/model_68x/microcode_blob.c
@@ -1,3 +1,3 @@
unsigned microcode_updates_68x[] = {
- #include "../../../../3rdparty/cpu/intel/model_68x/microcode.h"
+ #include "../../../../blobs/cpu/intel/model_68x/microcode.h"
};
diff --git a/src/cpu/intel/model_69x/microcode_blob.c b/src/cpu/intel/model_69x/microcode_blob.c
index a06c85939..37e19f3c1 100644
--- a/src/cpu/intel/model_69x/microcode_blob.c
+++ b/src/cpu/intel/model_69x/microcode_blob.c
@@ -1,3 +1,3 @@
unsigned microcode_updates_69x[] = {
- #include "../../../../3rdparty/cpu/intel/model_69x/microcode.h"
+ #include "../../../../blobs/cpu/intel/model_69x/microcode.h"
};
diff --git a/src/cpu/intel/model_6bx/microcode_blob.c b/src/cpu/intel/model_6bx/microcode_blob.c
index debd65064..cf5a95a47 100644
--- a/src/cpu/intel/model_6bx/microcode_blob.c
+++ b/src/cpu/intel/model_6bx/microcode_blob.c
@@ -1,3 +1,3 @@
unsigned microcode_updates_6bx[] = {
- #include "../../../../3rdparty/cpu/intel/model_6bx/microcode.h"
+ #include "../../../../blobs/cpu/intel/model_6bx/microcode.h"
};
diff --git a/src/cpu/intel/model_6dx/microcode_blob.c b/src/cpu/intel/model_6dx/microcode_blob.c
index 8f13d1b16..4871c7c80 100644
--- a/src/cpu/intel/model_6dx/microcode_blob.c
+++ b/src/cpu/intel/model_6dx/microcode_blob.c
@@ -1,3 +1,3 @@
unsigned microcode_updates_6dx[] = {
- #include "../../../../3rdparty/cpu/intel/model_6dx/microcode.h"
+ #include "../../../../blobs/cpu/intel/model_6dx/microcode.h"
};
diff --git a/src/cpu/intel/model_6ex/microcode_blob.c b/src/cpu/intel/model_6ex/microcode_blob.c
index e270059a4..2068a1dc6 100644
--- a/src/cpu/intel/model_6ex/microcode_blob.c
+++ b/src/cpu/intel/model_6ex/microcode_blob.c
@@ -1,3 +1,3 @@
unsigned microcode_updates_6ex[] = {
- #include "../../../../3rdparty/cpu/intel/model_6ex/microcode.h"
+ #include "../../../../blobs/cpu/intel/model_6ex/microcode.h"
};
diff --git a/src/cpu/intel/model_6fx/microcode_blob.c b/src/cpu/intel/model_6fx/microcode_blob.c
index 67a10cd28..371f9760e 100644
--- a/src/cpu/intel/model_6fx/microcode_blob.c
+++ b/src/cpu/intel/model_6fx/microcode_blob.c
@@ -1,3 +1,3 @@
unsigned microcode_updates_6fx[] = {
- #include "../../../../3rdparty/cpu/intel/model_6fx/microcode.h"
+ #include "../../../../blobs/cpu/intel/model_6fx/microcode.h"
};
diff --git a/src/cpu/intel/model_6xx/microcode_blob.c b/src/cpu/intel/model_6xx/microcode_blob.c
index ab082da66..489de4b81 100644
--- a/src/cpu/intel/model_6xx/microcode_blob.c
+++ b/src/cpu/intel/model_6xx/microcode_blob.c
@@ -1,3 +1,3 @@
unsigned microcode_updates_6xx[] = {
- #include "../../../../3rdparty/cpu/intel/model_6xx/microcode.h"
+ #include "../../../../blobs/cpu/intel/model_6xx/microcode.h"
};
diff --git a/src/cpu/intel/model_f0x/microcode_blob.c b/src/cpu/intel/model_f0x/microcode_blob.c
index 96577facf..32ca360ea 100644
--- a/src/cpu/intel/model_f0x/microcode_blob.c
+++ b/src/cpu/intel/model_f0x/microcode_blob.c
@@ -1,4 +1,4 @@
/* 256KB cache */
unsigned microcode_updates_f0x[] = {
- #include "../../../../3rdparty/cpu/intel/model_f0x/microcode.h"
+ #include "../../../../blobs/cpu/intel/model_f0x/microcode.h"
};
diff --git a/src/cpu/intel/model_f1x/microcode_blob.c b/src/cpu/intel/model_f1x/microcode_blob.c
index bf2fe92bb..63af4a356 100644
--- a/src/cpu/intel/model_f1x/microcode_blob.c
+++ b/src/cpu/intel/model_f1x/microcode_blob.c
@@ -1,4 +1,4 @@
/* 256KB cache */
unsigned microcode_updates_f1x[] = {
- #include "../../../../3rdparty/cpu/intel/model_f1x/microcode.h"
+ #include "../../../../blobs/cpu/intel/model_f1x/microcode.h"
};
diff --git a/src/cpu/intel/model_f2x/microcode_blob.c b/src/cpu/intel/model_f2x/microcode_blob.c
index 55133f2c7..6a5eee7bf 100644
--- a/src/cpu/intel/model_f2x/microcode_blob.c
+++ b/src/cpu/intel/model_f2x/microcode_blob.c
@@ -1,4 +1,4 @@
/* 512KB cache */
unsigned microcode_updates_f2x[] = {
- #include "../../../../3rdparty/cpu/intel/model_f2x/microcode.h"
+ #include "../../../../blobs/cpu/intel/model_f2x/microcode.h"
};
diff --git a/src/cpu/intel/model_f3x/microcode_blob.c b/src/cpu/intel/model_f3x/microcode_blob.c
index 80a0af7c6..d93912f93 100644
--- a/src/cpu/intel/model_f3x/microcode_blob.c
+++ b/src/cpu/intel/model_f3x/microcode_blob.c
@@ -1,3 +1,3 @@
unsigned microcode_updates_f3x[] = {
- #include "../../../../3rdparty/cpu/intel/model_f3x/microcode.h"
+ #include "../../../../blobs/cpu/intel/model_f3x/microcode.h"
};
diff --git a/src/cpu/intel/model_f4x/microcode_blob.c b/src/cpu/intel/model_f4x/microcode_blob.c
index 2d9850897..3ec447967 100644
--- a/src/cpu/intel/model_f4x/microcode_blob.c
+++ b/src/cpu/intel/model_f4x/microcode_blob.c
@@ -1,3 +1,3 @@
unsigned microcode_updates_f4x[] = {
- #include "../../../../3rdparty/cpu/intel/model_f4x/microcode.h"
+ #include "../../../../blobs/cpu/intel/model_f4x/microcode.h"
};
diff --git a/src/cpu/samsung/exynos5250/update-bl1.sh b/src/cpu/samsung/exynos5250/update-bl1.sh
index e47b25db9..755239992 100644
--- a/src/cpu/samsung/exynos5250/update-bl1.sh
+++ b/src/cpu/samsung/exynos5250/update-bl1.sh
@@ -1,7 +1,7 @@
#!/bin/sh
BL1_NAME="E5250.nbl1.bin"
-BL1_PATH="3rdparty/cpu/samsung/exynos5250/"
+BL1_PATH="blobs/cpu/samsung/exynos5250/"
BL1_URL="http://commondatastorage.googleapis.com/chromeos-localmirror/distfiles/exynos-pre-boot-0.0.2-r8.tbz2"
get_bl1() {
diff --git a/src/mainboard/amd/lamar/Kconfig b/src/mainboard/amd/lamar/Kconfig
index 338a675d3..55f0e206d 100644
--- a/src/mainboard/amd/lamar/Kconfig
+++ b/src/mainboard/amd/lamar/Kconfig
@@ -79,7 +79,7 @@ config ONBOARD_VGA_IS_PRIMARY
config HUDSON_XHCI_FWM_FILE
string
- default "3rdparty/southbridge/amd/bolton/xhci.bin"
+ default "blobs/southbridge/amd/bolton/xhci.bin"
config AZ_PIN
hex
diff --git a/src/northbridge/amd/pi/00630F01/Kconfig b/src/northbridge/amd/pi/00630F01/Kconfig
index 4e71895e4..6e8ebd055 100644
--- a/src/northbridge/amd/pi/00630F01/Kconfig
+++ b/src/northbridge/amd/pi/00630F01/Kconfig
@@ -48,6 +48,6 @@ config VGA_BIOS_ID
config VGA_BIOS_FILE
string
- default "3rdparty/northbridge/amd/00630F01/VBIOS.bin"
+ default "blobs/northbridge/amd/00630F01/VBIOS.bin"
endif
diff --git a/src/northbridge/amd/pi/00730F01/Kconfig b/src/northbridge/amd/pi/00730F01/Kconfig
index ab605f396..ec78dfb59 100644
--- a/src/northbridge/amd/pi/00730F01/Kconfig
+++ b/src/northbridge/amd/pi/00730F01/Kconfig
@@ -49,6 +49,6 @@ config VGA_BIOS_ID
config VGA_BIOS_FILE
string
- default "3rdparty/northbridge/amd/00730F01/VBIOS.bin"
+ default "blobs/northbridge/amd/00730F01/VBIOS.bin"
endif
diff --git a/src/northbridge/intel/sandybridge/Kconfig b/src/northbridge/intel/sandybridge/Kconfig
index 11370f569..29e5d8c90 100644
--- a/src/northbridge/intel/sandybridge/Kconfig
+++ b/src/northbridge/intel/sandybridge/Kconfig
@@ -105,7 +105,7 @@ config HAVE_MRC
config MRC_FILE
string "Intel System Agent path and filename"
depends on HAVE_MRC
- default "3rdparty/northbridge/intel/sandybridge/systemagent-r6.bin"
+ default "blobs/northbridge/intel/sandybridge/systemagent-r6.bin"
help
The path and filename of the file to use as System Agent
binary.
diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig
index 0b3e1763f..13f60bdbd 100644
--- a/src/soc/intel/baytrail/Kconfig
+++ b/src/soc/intel/baytrail/Kconfig
@@ -75,7 +75,7 @@ if HAVE_MRC
config MRC_FILE
string "Intel memory refeference code path and filename"
- default "3rdparty/northbridge/intel/sandybridge/systemagent-r6.bin"
+ default "blobs/northbridge/intel/sandybridge/systemagent-r6.bin"
help
The path and filename of the file to use as System Agent
binary. Note that this points to the sandybridge binary file
@@ -174,7 +174,7 @@ config HAVE_ME_BIN
help
The Intel processor in the selected system requires a special firmware
for an integrated controller called Management Engine (ME). The ME
- firmware might be provided in coreboot's 3rdparty repository. If
+ firmware might be provided in coreboot's blobs repository. If
not and if you don't have the firmware elsewhere, you can still
build coreboot without it. In this case however, you'll have to make
sure that you don't overwrite your ME firmware on your flash ROM.
@@ -182,7 +182,7 @@ config HAVE_ME_BIN
config ME_BIN_PATH
string "Path to management engine firmware"
depends on HAVE_ME_BIN
- default "3rdparty/mainboard/$(MAINBOARDDIR)/me.bin"
+ default "blobs/mainboard/$(MAINBOARDDIR)/me.bin"
config HAVE_IFD_BIN
bool
@@ -223,7 +223,7 @@ config IFD_PLATFORM_SECTION
config IFD_BIN_PATH
string "Path to intel firmware descriptor"
depends on !BUILD_WITH_FAKE_IFD
- default "3rdparty/mainboard/$(MAINBOARDDIR)/descriptor.bin"
+ default "blobs/mainboard/$(MAINBOARDDIR)/descriptor.bin"
config HAVE_REFCODE_BLOB
depends on ARCH_X86
diff --git a/src/soc/intel/baytrail/microcode/microcode_blob.c b/src/soc/intel/baytrail/microcode/microcode_blob.c
index 7c7b6f10b..a651f978f 100644
--- a/src/soc/intel/baytrail/microcode/microcode_blob.c
+++ b/src/soc/intel/baytrail/microcode/microcode_blob.c
@@ -1,3 +1,3 @@
unsigned microcode[] = {
-#include "../../../../../3rdparty/soc/intel/baytrail/microcode_blob.h"
+#include "../../../../../blobs/soc/intel/baytrail/microcode_blob.h"
};
diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig
index 6cec3dba4..d3c7ff659 100644
--- a/src/soc/intel/broadwell/Kconfig
+++ b/src/soc/intel/broadwell/Kconfig
@@ -211,7 +211,7 @@ config HAVE_ME_BIN
help
The Intel processor in the selected system requires a special firmware
for an integrated controller called Management Engine (ME). The ME
- firmware might be provided in coreboot's 3rdparty repository. If
+ firmware might be provided in coreboot's blobs repository. If
not and if you don't have the firmware elsewhere, you can still
build coreboot without it. In this case however, you'll have to make
sure that you don't overwrite your ME firmware on your flash ROM.
@@ -219,7 +219,7 @@ config HAVE_ME_BIN
config ME_BIN_PATH
string "Path to management engine firmware"
depends on HAVE_ME_BIN
- default "3rdparty/mainboard/$(MAINBOARDDIR)/me.bin"
+ default "blobs/mainboard/$(MAINBOARDDIR)/me.bin"
config HAVE_IFD_BIN
bool "Use Intel Firmware Descriptor from existing binary"
@@ -260,7 +260,7 @@ config IFD_PLATFORM_SECTION
config IFD_BIN_PATH
string "Path to intel firmware descriptor"
depends on !BUILD_WITH_FAKE_IFD
- default "3rdparty/mainboard/$(MAINBOARDDIR)/descriptor.bin"
+ default "blobs/mainboard/$(MAINBOARDDIR)/descriptor.bin"
config LOCK_MANAGEMENT_ENGINE
bool "Lock Management Engine section"
diff --git a/src/soc/intel/broadwell/microcode/microcode_blob.c b/src/soc/intel/broadwell/microcode/microcode_blob.c
index cd7fad606..93a6aa86e 100644
--- a/src/soc/intel/broadwell/microcode/microcode_blob.c
+++ b/src/soc/intel/broadwell/microcode/microcode_blob.c
@@ -18,6 +18,6 @@
*/
unsigned microcode[] = {
-#include "../../../../../3rdparty/soc/intel/broadwell/microcode_blob.h"
+#include "../../../../../blobs/soc/intel/broadwell/microcode_blob.h"
};
diff --git a/src/soc/nvidia/tegra132/Kconfig b/src/soc/nvidia/tegra132/Kconfig
index fc321025d..af8f61751 100644
--- a/src/soc/nvidia/tegra132/Kconfig
+++ b/src/soc/nvidia/tegra132/Kconfig
@@ -49,7 +49,7 @@ config MAX_CPUS
config MTS_DIRECTORY
string "Directory where MTS microcode files are located"
- default "3rdparty/cpu/nvidia/tegra132/current/prod"
+ default "blobs/cpu/nvidia/tegra132/current/prod"
help
Path to directory where MTS microcode files are located.
diff --git a/src/soc/qualcomm/ipq806x/Kconfig b/src/soc/qualcomm/ipq806x/Kconfig
index 5c03d5257..c1c66bb8c 100644
--- a/src/soc/qualcomm/ipq806x/Kconfig
+++ b/src/soc/qualcomm/ipq806x/Kconfig
@@ -30,7 +30,7 @@ config MBN_ENCAPSULATION
config SBL_BLOB
depends on USE_BLOBS
string "file name of the Qualcomm SBL blob"
- default "3rdparty/cpu/qualcomm/ipq806x/uber-sbl.mbn"
+ default "blobs/cpu/qualcomm/ipq806x/uber-sbl.mbn"
help
The path and filename of the binary blob containing
ipq806x early initialization code, as supplied by the
diff --git a/src/soc/qualcomm/ipq806x/Makefile.inc b/src/soc/qualcomm/ipq806x/Makefile.inc
index 8cf8d7aa5..f3b0b200a 100644
--- a/src/soc/qualcomm/ipq806x/Makefile.inc
+++ b/src/soc/qualcomm/ipq806x/Makefile.inc
@@ -83,7 +83,7 @@ CPPFLAGS_common += -Isrc/soc/qualcomm/ipq806x/include
mbn-files := cdt.mbn ddr.mbn rpm.mbn tz.mbn
# Location of the binary blobs
-mbn-root := 3rdparty/cpu/qualcomm/ipq806x
+mbn-root := blobs/cpu/qualcomm/ipq806x
# Create make variables to aid cbfs-files-handler in processing the blobs (add
# them all as raw binaries at the root level).
diff --git a/src/soc/samsung/exynos5250/Makefile.inc b/src/soc/samsung/exynos5250/Makefile.inc
index 1cde34950..c09ecb408 100644
--- a/src/soc/samsung/exynos5250/Makefile.inc
+++ b/src/soc/samsung/exynos5250/Makefile.inc
@@ -52,6 +52,6 @@ $(objcbfs)/bootblock.raw.elf: $(objcbfs)/bootblock.elf
$(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin
@printf " BL1, CKSUM $(subst $(obj)/,,$(@))\n"
util/exynos/fixed_cksum.py $< $<.cksum 32768
- cat 3rdparty/cpu/samsung/exynos5250/bl1.bin $<.cksum > $@
+ cat blobs/cpu/samsung/exynos5250/bl1.bin $<.cksum > $@
endif
diff --git a/src/soc/samsung/exynos5420/Makefile.inc b/src/soc/samsung/exynos5420/Makefile.inc
index e42fc9aeb..8d90ba07c 100644
--- a/src/soc/samsung/exynos5420/Makefile.inc
+++ b/src/soc/samsung/exynos5420/Makefile.inc
@@ -54,6 +54,6 @@ $(objcbfs)/bootblock.raw.elf: $(objcbfs)/bootblock.elf
$(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin
@printf " BL1, CKSUM $(subst $(obj)/,,$(@))\n"
util/exynos/variable_cksum.py $< $<.cksum
- cat 3rdparty/cpu/samsung/exynos5420/bl1.bin $<.cksum > $@
+ cat blobs/cpu/samsung/exynos5420/bl1.bin $<.cksum > $@
endif
diff --git a/src/southbridge/amd/agesa/hudson/Kconfig b/src/southbridge/amd/agesa/hudson/Kconfig
index acc2d7255..9a05c1ad2 100644
--- a/src/southbridge/amd/agesa/hudson/Kconfig
+++ b/src/southbridge/amd/agesa/hudson/Kconfig
@@ -74,20 +74,20 @@ config HUDSON_GEC_FWM
config HUDSON_XHCI_FWM_FILE
string "XHCI firmware path and filename"
- default "3rdparty/southbridge/amd/hudson/xhci.bin" if SOUTHBRIDGE_AMD_AGESA_HUDSON
- default "3rdparty/southbridge/amd/yangtze/xhci.bin" if SOUTHBRIDGE_AMD_AGESA_YANGTZE
+ default "blobs/southbridge/amd/hudson/xhci.bin" if SOUTHBRIDGE_AMD_AGESA_HUDSON
+ default "blobs/southbridge/amd/yangtze/xhci.bin" if SOUTHBRIDGE_AMD_AGESA_YANGTZE
depends on HUDSON_XHCI_FWM
config HUDSON_IMC_FWM_FILE
string "IMC firmware path and filename"
- default "3rdparty/southbridge/amd/hudson/imc.bin" if SOUTHBRIDGE_AMD_AGESA_HUDSON
- default "3rdparty/southbridge/amd/yangtze/imc.bin" if SOUTHBRIDGE_AMD_AGESA_YANGTZE
+ default "blobs/southbridge/amd/hudson/imc.bin" if SOUTHBRIDGE_AMD_AGESA_HUDSON
+ default "blobs/southbridge/amd/yangtze/imc.bin" if SOUTHBRIDGE_AMD_AGESA_YANGTZE
depends on HUDSON_IMC_FWM
config HUDSON_GEC_FWM_FILE
string "GEC firmware path and filename"
- default "3rdparty/southbridge/amd/hudson/gec.bin" if SOUTHBRIDGE_AMD_AGESA_HUDSON
- default "3rdparty/southbridge/amd/yangtze/gec.bin" if SOUTHBRIDGE_AMD_AGESA_YANGTZE
+ default "blobs/southbridge/amd/hudson/gec.bin" if SOUTHBRIDGE_AMD_AGESA_HUDSON
+ default "blobs/southbridge/amd/yangtze/gec.bin" if SOUTHBRIDGE_AMD_AGESA_YANGTZE
depends on HUDSON_GEC_FWM
config HUDSON_FWM
diff --git a/src/southbridge/amd/agesa/hudson/Makefile.inc b/src/southbridge/amd/agesa/hudson/Makefile.inc
index bcadd8ddf..8875036ea 100644
--- a/src/southbridge/amd/agesa/hudson/Makefile.inc
+++ b/src/southbridge/amd/agesa/hudson/Makefile.inc
@@ -89,7 +89,7 @@ cbfs-files-y += hudson/xhci
hudson/xhci-file := $(call strip_quotes, $(CONFIG_HUDSON_XHCI_FWM_FILE))
hudson/xhci-position := $(HUDSON_XHCI_POSITION)
hudson/xhci-type := raw
-hudson/xhci-required := Hudson XHCI firmware (available in coreboot/3rdparty if enabled)
+hudson/xhci-required := Hudson XHCI firmware (available in coreboot/blobs if enabled)
endif
ifeq ($(CONFIG_HUDSON_IMC_FWM), y)
@@ -97,7 +97,7 @@ cbfs-files-y += hudson/imc
hudson/imc-file := $(call strip_quotes, $(CONFIG_HUDSON_IMC_FWM_FILE))
hudson/imc-position := $(HUDSON_IMC_POSITION)
hudson/imc-type := raw
-hudson/imc-required := Hudson IMC Firmware (available in coreboot/3rdparty if enabled)
+hudson/imc-required := Hudson IMC Firmware (available in coreboot/blobs if enabled)
endif
ifeq ($(CONFIG_HUDSON_GEC_FWM), y)
diff --git a/src/southbridge/amd/cimx/sb800/Kconfig b/src/southbridge/amd/cimx/sb800/Kconfig
index 891a8e096..5a0980ac9 100644
--- a/src/southbridge/amd/cimx/sb800/Kconfig
+++ b/src/southbridge/amd/cimx/sb800/Kconfig
@@ -134,7 +134,7 @@ if SB800_IMC_FWM
config SB800_IMC_FWM_FILE
string "IMC firmware path and filename"
- default "3rdparty/southbridge/amd/sb800/imc.bin"
+ default "blobs/southbridge/amd/sb800/imc.bin"
choice
prompt "SB800 Firmware ROM Position"
diff --git a/src/southbridge/amd/pi/hudson/Kconfig b/src/southbridge/amd/pi/hudson/Kconfig
index 9d1010f3a..206070025 100644
--- a/src/southbridge/amd/pi/hudson/Kconfig
+++ b/src/southbridge/amd/pi/hudson/Kconfig
@@ -83,12 +83,12 @@ config HUDSON_PSP
config HUDSON_XHCI_FWM_FILE
string "XHCI firmware path and filename"
- default "3rdparty/southbridge/amd/avalon/xhci.bin" if SOUTHBRIDGE_AMD_PI_AVALON
+ default "blobs/southbridge/amd/avalon/xhci.bin" if SOUTHBRIDGE_AMD_PI_AVALON
depends on HUDSON_XHCI_FWM
config HUDSON_IMC_FWM_FILE
string "IMC firmware path and filename"
- default "3rdparty/southbridge/amd/avalon/imc.bin" if SOUTHBRIDGE_AMD_PI_AVALON
+ default "blobs/southbridge/amd/avalon/imc.bin" if SOUTHBRIDGE_AMD_PI_AVALON
depends on HUDSON_IMC_FWM
config HUDSON_GEC_FWM_FILE
@@ -126,7 +126,7 @@ endif # HUDSON_FWM
config AMD_PUBKEY_FILE
depends on HUDSON_PSP
string "AMD public Key"
- default "3rdparty/southbridge/amd/avalon/PSP/AmdPubKey.bin" if CPU_AMD_PI_00730F01
+ default "blobs/southbridge/amd/avalon/PSP/AmdPubKey.bin" if CPU_AMD_PI_00730F01
config HUDSON_SATA_MODE
int "SATA Mode"
diff --git a/src/southbridge/amd/pi/hudson/Makefile.inc b/src/southbridge/amd/pi/hudson/Makefile.inc
index c66d54104..4c36e6623 100644
--- a/src/southbridge/amd/pi/hudson/Makefile.inc
+++ b/src/southbridge/amd/pi/hudson/Makefile.inc
@@ -133,7 +133,7 @@ cbfs-files-y += fch/xhci
fch/xhci-file := $(call strip_quotes, $(CONFIG_HUDSON_XHCI_FWM_FILE))
fch/xhci-position := $(HUDSON_XHCI_POSITION)
fch/xhci-type := raw
-fch/xhci-required := Hudson XHCI firmware (available in coreboot/3rdparty if enabled)
+fch/xhci-required := Hudson XHCI firmware (available in coreboot/blobs if enabled)
endif
ifeq ($(CONFIG_HUDSON_IMC_FWM), y)
@@ -141,7 +141,7 @@ cbfs-files-y += fch/imc
fch/imc-file := $(call strip_quotes, $(CONFIG_HUDSON_IMC_FWM_FILE))
fch/imc-position := $(HUDSON_IMC_POSITION)
fch/imc-type := raw
-fch/imc-required := Hudson IMC Firmware (available in coreboot/3rdparty if enabled)
+fch/imc-required := Hudson IMC Firmware (available in coreboot/blobs if enabled)
endif
ifeq ($(CONFIG_HUDSON_GEC_FWM), y)
diff --git a/src/southbridge/intel/bd82x6x/Kconfig b/src/southbridge/intel/bd82x6x/Kconfig
index 970605c5e..11edd9dfc 100644
--- a/src/southbridge/intel/bd82x6x/Kconfig
+++ b/src/southbridge/intel/bd82x6x/Kconfig
@@ -106,7 +106,7 @@ config IFD_PLATFORM_SECTION
config IFD_BIN_PATH
string "Path to intel firmware descriptor"
depends on !BUILD_WITH_FAKE_IFD
- default "3rdparty/mainboard/$(MAINBOARDDIR)/descriptor.bin"
+ default "blobs/mainboard/$(MAINBOARDDIR)/descriptor.bin"
config HAVE_GBE_BIN
bool "Add gigabit ethernet firmware"
@@ -119,7 +119,7 @@ config HAVE_GBE_BIN
config GBE_BIN_PATH
string "Path to gigabit ethernet firmware"
depends on HAVE_GBE_BIN
- default "3rdparty/mainboard/$(MAINBOARDDIR)/gbe.bin"
+ default "blobs/mainboard/$(MAINBOARDDIR)/gbe.bin"
config HAVE_ME_BIN
bool "Add Intel Management Engine firmware"
@@ -127,7 +127,7 @@ config HAVE_ME_BIN
help
The Intel processor in the selected system requires a special firmware
for an integrated controller called Management Engine (ME). The ME
- firmware might be provided in coreboot's 3rdparty repository. If
+ firmware might be provided in coreboot's blobs repository. If
not and if you don't have the firmware elsewhere, you can still
build coreboot without it. In this case however, you'll have to make
sure that you don't overwrite your ME firmware on your flash ROM.
@@ -135,7 +135,7 @@ config HAVE_ME_BIN
config ME_BIN_PATH
string "Path to management engine firmware"
depends on HAVE_ME_BIN
- default "3rdparty/mainboard/$(MAINBOARDDIR)/me.bin"
+ default "blobs/mainboard/$(MAINBOARDDIR)/me.bin"
config LOCK_MANAGEMENT_ENGINE
bool "Lock Management Engine section"
diff --git a/src/southbridge/intel/ibexpeak/Kconfig b/src/southbridge/intel/ibexpeak/Kconfig
index b47bf992f..9bdde6934 100644
--- a/src/southbridge/intel/ibexpeak/Kconfig
+++ b/src/southbridge/intel/ibexpeak/Kconfig
@@ -87,7 +87,7 @@ config IFD_ME_SECTION
config IFD_BIN_PATH
string "Path to intel firmware descriptor"
depends on !BUILD_WITH_FAKE_IFD
- default "3rdparty/mainboard/$(MAINBOARDDIR)/descriptor.bin"
+ default "blobs/mainboard/$(MAINBOARDDIR)/descriptor.bin"
config HAVE_ME_BIN
@@ -96,7 +96,7 @@ config HAVE_ME_BIN
help
The Intel processor in the selected system requires a special firmware
for an integrated controller called Management Engine (ME). The ME
- firmware might be provided in coreboot's 3rdparty repository. If
+ firmware might be provided in coreboot's blobs repository. If
not and if you don't have the firmware elsewhere, you can still
build coreboot without it. In this case however, you'll have to make
sure that you don't overwrite your ME firmware on your flash ROM.
@@ -104,7 +104,7 @@ config HAVE_ME_BIN
config ME_BIN_PATH
string "Path to management engine firmware"
depends on HAVE_ME_BIN
- default "3rdparty/mainboard/$(MAINBOARDDIR)/me.bin"
+ default "blobs/mainboard/$(MAINBOARDDIR)/me.bin"
config HPET_MIN_TICKS
hex
diff --git a/src/southbridge/intel/lynxpoint/Kconfig b/src/southbridge/intel/lynxpoint/Kconfig
index 4797e96af..500d79ae8 100644
--- a/src/southbridge/intel/lynxpoint/Kconfig
+++ b/src/southbridge/intel/lynxpoint/Kconfig
@@ -98,7 +98,7 @@ config IFD_PLATFORM_SECTION
config IFD_BIN_PATH
string "Path to intel firmware descriptor"
depends on !BUILD_WITH_FAKE_IFD
- default "3rdparty/mainboard/$(MAINBOARDDIR)/descriptor.bin"
+ default "blobs/mainboard/$(MAINBOARDDIR)/descriptor.bin"
config HAVE_ME_BIN
bool "Add Intel Management Engine firmware"
@@ -106,7 +106,7 @@ config HAVE_ME_BIN
help
The Intel processor in the selected system requires a special firmware
for an integrated controller called Management Engine (ME). The ME
- firmware might be provided in coreboot's 3rdparty repository. If
+ firmware might be provided in coreboot's blobs repository. If
not and if you don't have the firmware elsewhere, you can still
build coreboot without it. In this case however, you'll have to make
sure that you don't overwrite your ME firmware on your flash ROM.
@@ -114,7 +114,7 @@ config HAVE_ME_BIN
config ME_BIN_PATH
string "Path to management engine firmware"
depends on HAVE_ME_BIN
- default "3rdparty/mainboard/$(MAINBOARDDIR)/me.bin"
+ default "blobs/mainboard/$(MAINBOARDDIR)/me.bin"
config ME_MBP_CLEAR_LATE
bool "Defer wait for ME MBP Cleared"
diff --git a/src/vendorcode/amd/Kconfig b/src/vendorcode/amd/Kconfig
index d9ac73127..49969ec1a 100644
--- a/src/vendorcode/amd/Kconfig
+++ b/src/vendorcode/amd/Kconfig
@@ -37,7 +37,7 @@ config CPU_AMD_AGESA_BINARY_PI
select HUDSON_DISABLE_IMC
help
Use a binary PI package. Generally, these will be stored in the
- "3rdparty" directory. For some processors, these must be obtained
+ "blobs" directory. For some processors, these must be obtained
directly from AMD Embedded Processors Group
(http://www.amdcom/embedded).
diff --git a/src/vendorcode/amd/pi/00630F01/Kconfig b/src/vendorcode/amd/pi/00630F01/Kconfig
index bd49990cd..0e66066c7 100644
--- a/src/vendorcode/amd/pi/00630F01/Kconfig
+++ b/src/vendorcode/amd/pi/00630F01/Kconfig
@@ -35,7 +35,7 @@ config AGESA_BINARY_PI_DEFAULTS # dummy
config AGESA_BINARY_PI_PATH_DEFAULT
string
- default "3rdparty/pi/amd/00630F01"
+ default "blobs/pi/amd/00630F01"
help
The default binary file name to use for AMD platform initialization.
diff --git a/src/vendorcode/amd/pi/00730F01/Kconfig b/src/vendorcode/amd/pi/00730F01/Kconfig
index c630a24e0..f9dfd72e4 100644
--- a/src/vendorcode/amd/pi/00730F01/Kconfig
+++ b/src/vendorcode/amd/pi/00730F01/Kconfig
@@ -35,7 +35,7 @@ config AGESA_BINARY_PI_DEFAULTS # dummy
config AGESA_BINARY_PI_PATH_DEFAULT
string
- default "3rdparty/pi/amd/00730F01"
+ default "blobs/pi/amd/00730F01"
help
The default binary file name to use for AMD platform initialization.
diff --git a/src/vendorcode/google/chromeos/build-snow b/src/vendorcode/google/chromeos/build-snow
index da1566bf1..00fbec174 100755
--- a/src/vendorcode/google/chromeos/build-snow
+++ b/src/vendorcode/google/chromeos/build-snow
@@ -8,7 +8,7 @@ TMP_DIFF="$SCRIPT_DIR/.image-diff.bin"
FLASHROM="/usr/local/sbin/flashrom"
BL1_NAME="E5250.nbl1.bin"
-BL1_PATH="3rdparty/cpu/samsung/exynos5250/"
+BL1_PATH="blobs/cpu/samsung/exynos5250/"
BL1_URL="http://commondatastorage.googleapis.com/chromeos-localmirror/distfiles/exynos-pre-boot-0.0.2-r8.tbz2"
die() {