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-rw-r--r--src/include/cpu/x86/smm.h1
-rw-r--r--src/soc/intel/baytrail/Makefile.inc1
-rw-r--r--src/soc/intel/baytrail/smihandler.c59
3 files changed, 61 insertions, 0 deletions
diff --git a/src/include/cpu/x86/smm.h b/src/include/cpu/x86/smm.h
index c16a6c50d..adaf74b7a 100644
--- a/src/include/cpu/x86/smm.h
+++ b/src/include/cpu/x86/smm.h
@@ -460,6 +460,7 @@ typedef struct {
#define APM_CNT_MBI_UPDATE 0xeb
#define APM_CNT_GNVS_UPDATE 0xea
#define APM_CNT_FINALIZE 0xcb
+#define APM_CNT_LEGACY 0xcc
#define APM_STS 0xb3
/* SMI handler function prototypes */
diff --git a/src/soc/intel/baytrail/Makefile.inc b/src/soc/intel/baytrail/Makefile.inc
index 67ad00beb..6d28c7868 100644
--- a/src/soc/intel/baytrail/Makefile.inc
+++ b/src/soc/intel/baytrail/Makefile.inc
@@ -20,6 +20,7 @@ ramstage-y += chip.c
ramstage-y += gfx.c
ramstage-y += iosf.c
romstage-y += iosf.c
+smm-y += iosf.c
ramstage-y += northcluster.c
ramstage-y += ramstage.c
ramstage-y += gpio.c
diff --git a/src/soc/intel/baytrail/smihandler.c b/src/soc/intel/baytrail/smihandler.c
index 03842b2fb..3fac52506 100644
--- a/src/soc/intel/baytrail/smihandler.c
+++ b/src/soc/intel/baytrail/smihandler.c
@@ -28,6 +28,7 @@
#include <halt.h>
#include <spi-generic.h>
+#include <soc/iosf.h>
#include <soc/pci_devs.h>
#include <soc/pmc.h>
#include <soc/nvs.h>
@@ -250,6 +251,60 @@ static void finalize(void)
#endif
}
+/*
+ * soc_legacy: A payload (Depthcharge) has indicated that the
+ * legacy payload (SeaBIOS) is being loaded. Switch devices that are
+ * in ACPI mode to PCI mode so that non-ACPI drivers may work.
+ *
+ */
+static void soc_legacy(void)
+{
+ u32 reg32;
+
+ /* LPE Device */
+ if (gnvs->dev.lpe_en) {
+ reg32 = iosf_port58_read(LPE_PCICFGCTR1);
+ reg32 &=
+ ~(LPE_PCICFGCTR1_PCI_CFG_DIS | LPE_PCICFGCTR1_ACPI_INT_EN);
+ iosf_port58_write(LPE_PCICFGCTR1, reg32);
+ }
+
+ /* SCC Devices */
+#define SCC_ACPI_MODE_DISABLE(name_) \
+ do { if (gnvs->dev.scc_en[SCC_NVS_ ## name_]) { \
+ reg32 = iosf_scc_read(SCC_ ## name_ ## _CTL); \
+ reg32 &= ~(SCC_CTL_PCI_CFG_DIS | SCC_CTL_ACPI_INT_EN); \
+ iosf_scc_write(SCC_ ## name_ ## _CTL, reg32); \
+ } } while (0)
+
+ SCC_ACPI_MODE_DISABLE(MMC);
+ SCC_ACPI_MODE_DISABLE(SD);
+ SCC_ACPI_MODE_DISABLE(SDIO);
+
+ /* LPSS Devices */
+#define LPSS_ACPI_MODE_DISABLE(name_) \
+ do { if (gnvs->dev.lpss_en[LPSS_NVS_ ## name_]) { \
+ reg32 = iosf_lpss_read(LPSS_ ## name_ ## _CTL); \
+ reg32 &= ~LPSS_CTL_PCI_CFG_DIS | ~LPSS_CTL_ACPI_INT_EN; \
+ iosf_lpss_write(LPSS_ ## name_ ## _CTL, reg32); \
+ } } while (0)
+
+ LPSS_ACPI_MODE_DISABLE(SIO_DMA1);
+ LPSS_ACPI_MODE_DISABLE(I2C1);
+ LPSS_ACPI_MODE_DISABLE(I2C2);
+ LPSS_ACPI_MODE_DISABLE(I2C3);
+ LPSS_ACPI_MODE_DISABLE(I2C4);
+ LPSS_ACPI_MODE_DISABLE(I2C5);
+ LPSS_ACPI_MODE_DISABLE(I2C6);
+ LPSS_ACPI_MODE_DISABLE(I2C7);
+ LPSS_ACPI_MODE_DISABLE(SIO_DMA2);
+ LPSS_ACPI_MODE_DISABLE(PWM1);
+ LPSS_ACPI_MODE_DISABLE(PWM2);
+ LPSS_ACPI_MODE_DISABLE(HSUART1);
+ LPSS_ACPI_MODE_DISABLE(HSUART2);
+ LPSS_ACPI_MODE_DISABLE(SPI);
+}
+
static void southbridge_smi_apmc(void)
{
uint8_t reg8;
@@ -303,6 +358,10 @@ static void southbridge_smi_apmc(void)
case APM_CNT_FINALIZE:
finalize();
break;
+
+ case APM_CNT_LEGACY:
+ soc_legacy();
+ break;
}
mainboard_smi_apmc(reg8);