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-rw-r--r--Makefile.inc10
-rw-r--r--src/include/romstage_handoff.h2
-rw-r--r--src/soc/rockchip/rk3288/media.c2
-rw-r--r--src/soc/samsung/exynos5250/alternate_cbfs.h2
-rw-r--r--src/soc/samsung/exynos5250/gpio.c7
-rw-r--r--src/soc/samsung/exynos5420/alternate_cbfs.h2
-rw-r--r--src/soc/samsung/exynos5420/gpio.c7
-rw-r--r--src/vendorcode/google/chromeos/chromeos.c2
8 files changed, 10 insertions, 24 deletions
diff --git a/Makefile.inc b/Makefile.inc
index d444457a2..ea2553f09 100644
--- a/Makefile.inc
+++ b/Makefile.inc
@@ -116,12 +116,14 @@ ramstage-postprocess=$(foreach d,$(sort $(dir $(filter-out %.ld,$(1)))), \
$(eval $(d)ramstage.o: $(call files-in-dir,$(d),$(filter-out %.ld,$(1))); $$(LD_ramstage) -o $$@ -r $$^ ) \
$(eval ramstage-objs:=$(d)ramstage.o $(filter-out $(filter-out %.ld, $(call files-in-dir,$(d),$(1))),$(ramstage-objs))))
-romstage-generic-ccopts += -D__PRE_RAM__
+bootblock-generic-ccopts += -D__PRE_RAM__ -D__BOOTBLOCK__
+romstage-generic-ccopts += -D__PRE_RAM__ -D__ROMSTAGE__
+ramstage-generic-ccopts += -D__RAMSTAGE__
ifeq ($(CONFIG_TRACE),y)
-ramstage-c-ccopts:= -finstrument-functions
+ramstage-c-ccopts += -finstrument-functions
endif
ifeq ($(CONFIG_COVERAGE),y)
-ramstage-c-ccopts+=-fprofile-arcs -ftest-coverage
+ramstage-c-ccopts += -fprofile-arcs -ftest-coverage
endif
# try to fetch non-optional submodules if the source is under git
@@ -132,8 +134,6 @@ ifeq ($(CONFIG_USE_BLOBS),y)
forgetthis:=$(if $(GIT),$(shell git submodule update --init --checkout 3rdparty))
endif
-bootblock-generic-ccopts += -D__BOOTBLOCK__ -D__PRE_RAM__
-
ramstage-c-deps:=$$(OPTION_TABLE_H)
romstage-c-deps:=$$(OPTION_TABLE_H)
verstage-c-deps:=$$(OPTION_TABLE_H)
diff --git a/src/include/romstage_handoff.h b/src/include/romstage_handoff.h
index 307babd32..e06d17c5a 100644
--- a/src/include/romstage_handoff.h
+++ b/src/include/romstage_handoff.h
@@ -40,7 +40,7 @@ struct romstage_handoff {
uint32_t ramstage_entry_point;
};
-#if defined(__PRE_RAM__)
+#if defined(__ROMSTAGE__)
#if CONFIG_EARLY_CBMEM_INIT
/* The romstage_handoff_find_or_add() function provides the necessary logic
* for initializing the romstage_handoff structure in cbmem. Different components
diff --git a/src/soc/rockchip/rk3288/media.c b/src/soc/rockchip/rk3288/media.c
index c6ceeb9cd..2b023e15d 100644
--- a/src/soc/rockchip/rk3288/media.c
+++ b/src/soc/rockchip/rk3288/media.c
@@ -24,7 +24,7 @@
int init_default_cbfs_media(struct cbfs_media *media)
{
-#if defined(__BOOT_BLOCK__) || defined(__VER_STAGE__)
+#if defined(__PRE_RAM__) && !defined(__ROMSTAGE__)
return initialize_rockchip_spi_cbfs_media(media,
(void *)CONFIG_CBFS_SRAM_CACHE_ADDRESS,
CONFIG_CBFS_SRAM_CACHE_SIZE);
diff --git a/src/soc/samsung/exynos5250/alternate_cbfs.h b/src/soc/samsung/exynos5250/alternate_cbfs.h
index 72a30acc8..a064b62e8 100644
--- a/src/soc/samsung/exynos5250/alternate_cbfs.h
+++ b/src/soc/samsung/exynos5250/alternate_cbfs.h
@@ -36,7 +36,7 @@ static u32 * const iram_secondary_base = (u32 *)0x02020018;
#define OM_STAT_SPI 0x14
#define OM_STAT_MASK 0x7f
-#if defined(__BOOT_BLOCK__)
+#if defined(__PRE_RAM__) && !defined(__ROMSTAGE__)
/* A small space in IRAM to hold the romstage-only image */
static void * const alternate_cbfs_buffer =
(void *)CONFIG_CBFS_CACHE_ADDRESS;
diff --git a/src/soc/samsung/exynos5250/gpio.c b/src/soc/samsung/exynos5250/gpio.c
index 3e50791ed..98c177d4d 100644
--- a/src/soc/samsung/exynos5250/gpio.c
+++ b/src/soc/samsung/exynos5250/gpio.c
@@ -211,12 +211,6 @@ int gpio_set_value(unsigned gpio, int value)
*/
#define GPIO_DELAY_US 5
-#ifndef __BOOTBLOCK__
-/*
- * FIXME(dhendrix): These functions use udelay, which has dependencies on
- * pwm code and timer code. These aren't necessary for the bootblock and
- * bloat the image significantly.
- */
int gpio_read_mvl3(unsigned gpio)
{
int high, low;
@@ -252,7 +246,6 @@ int gpio_read_mvl3(unsigned gpio)
return value;
}
-#endif /* __BOOTBLOCK__ */
/*
* Display Exynos GPIO information
diff --git a/src/soc/samsung/exynos5420/alternate_cbfs.h b/src/soc/samsung/exynos5420/alternate_cbfs.h
index af7751d4e..8122a25e8 100644
--- a/src/soc/samsung/exynos5420/alternate_cbfs.h
+++ b/src/soc/samsung/exynos5420/alternate_cbfs.h
@@ -36,7 +36,7 @@ static u32 * const iram_secondary_base = (u32 *)0x02020018;
#define OM_STAT_SPI 0x14
#define OM_STAT_MASK 0x7f
-#if defined(__BOOT_BLOCK__)
+#if defined(__PRE_RAM__) && !defined(__ROMSTAGE__)
/* A small space in IRAM to hold the romstage-only image */
static void * const alternate_cbfs_buffer =
(void *)CONFIG_CBFS_CACHE_ADDRESS;
diff --git a/src/soc/samsung/exynos5420/gpio.c b/src/soc/samsung/exynos5420/gpio.c
index ac82bf7eb..74d81135d 100644
--- a/src/soc/samsung/exynos5420/gpio.c
+++ b/src/soc/samsung/exynos5420/gpio.c
@@ -211,12 +211,6 @@ int gpio_set_value(unsigned gpio, int value)
*/
#define GPIO_DELAY_US 15
-#ifndef __BOOTBLOCK__
-/*
- * FIXME(dhendrix): These functions use udelay, which has dependencies on
- * pwm code and timer code. These aren't necessary for the bootblock and
- * bloat the image significantly.
- */
int gpio_read_mvl3(unsigned gpio)
{
int high, low;
@@ -252,7 +246,6 @@ int gpio_read_mvl3(unsigned gpio)
return value;
}
-#endif /* __BOOTBLOCK__ */
/*
* Display Exynos GPIO information
diff --git a/src/vendorcode/google/chromeos/chromeos.c b/src/vendorcode/google/chromeos/chromeos.c
index 3a499d56e..edaa0d9e7 100644
--- a/src/vendorcode/google/chromeos/chromeos.c
+++ b/src/vendorcode/google/chromeos/chromeos.c
@@ -107,7 +107,7 @@ int vboot_skip_display_init(void)
#endif
}
-#ifdef __PRE_RAM__
+#ifdef __ROMSTAGE__
void __attribute__((weak)) save_chromeos_gpios(void)
{
// Can be implemented by a mainboard