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authorPatrick Georgi <pgeorgi@chromium.org>2015-05-19 16:41:21 +0200
committerPatrick Georgi <pgeorgi@google.com>2015-05-19 20:30:04 +0200
commit8d6e24c739699c1e66434a03a781ba5b9efb1fba (patch)
tree874fcf32e92a9041c3cd7ce611645b7f92c00480 /util
parentd32b27383b35b62ea853e5edda5af302898c9cf2 (diff)
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cbfstool: clarify dependencies in Makefile
While logical, make's handling of multiple targets in a rule isn't intuitive, and was done wrong in cbfstool's Makefile. %.c %.h: %.l encourages make to run the rule twice, once to generate the .c file, once for the .h file. Hilarity ensues. Change-Id: I2560cb34b6aee5f4bdd764bb05bb69ea2789c7d8 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/10251 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'util')
-rw-r--r--util/cbfstool/Makefile8
1 files changed, 6 insertions, 2 deletions
diff --git a/util/cbfstool/Makefile b/util/cbfstool/Makefile
index 6e8235b49..65d571060 100644
--- a/util/cbfstool/Makefile
+++ b/util/cbfstool/Makefile
@@ -54,9 +54,13 @@ $(obj)/%: $(obj)/%.o
$(obj)/%.o: %.c
mkdir -p $(dir $@)
$(HOSTCC) $(CPPFLAGS) $(CFLAGS) -c -o $@ $<
-%.c %.h: %.l
+
+fmd_scanner.h: fmd_scanner.c
+fmd_scanner.c: fmd_scanner.l
$(LEX) $(LFLAGS) -t --header-file=$*.h $< >$*.c
-%.c %.h: %.y
+
+fmd_parser.h: fmd_parser.c
+fmd_parser.c: fmd_parser.y
$(YACC) $(YFLAGS) -d $<
mv -f y.tab.c $*.c
mv -f y.tab.h $*.h