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authorStefan Reinauer <stepan@coresystems.de>2009-10-28 16:52:48 +0000
committerStefan Reinauer <stepan@openbios.org>2009-10-28 16:52:48 +0000
commit1a08f582b54ec9fff0f356a824647ee40b3a5008 (patch)
tree32a14bd5bce84638628fabc01935486d7cccace2 /targets
parent581707811c1c24bb0676e7582c671548b8851436 (diff)
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preliminary Intel D945GCLF Atom+i945 support.
ram init fails, as the i945 driver currently only supports the mobile version of the chipset.. Not sure how much sense it makes to check this in, but since it's a nice and cheap board, maybe someone wants to work on this. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4879 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'targets')
-rw-r--r--targets/intel/d945gclf/Config-abuild.lb29
1 files changed, 29 insertions, 0 deletions
diff --git a/targets/intel/d945gclf/Config-abuild.lb b/targets/intel/d945gclf/Config-abuild.lb
new file mode 100644
index 000000000..743ee713e
--- /dev/null
+++ b/targets/intel/d945gclf/Config-abuild.lb
@@ -0,0 +1,29 @@
+# This will make a target directory of ./VENDOR_MAINBOARD
+
+target VENDOR_MAINBOARD
+mainboard VENDOR/MAINBOARD
+
+option CC="CROSSCC"
+option CONFIG_CROSS_COMPILE="CROSS_PREFIX"
+option HOSTCC="CROSS_HOSTCC"
+
+__COMPRESSION__
+__LOGLEVEL__
+
+option CONFIG_ROM_SIZE=512*1024
+
+romimage "normal"
+ option CONFIG_USE_FALLBACK_IMAGE=0
+ option COREBOOT_EXTRA_VERSION=".0-normal"
+ payload __PAYLOAD__
+end
+
+romimage "fallback"
+ option CONFIG_USE_FALLBACK_IMAGE=1
+ option COREBOOT_EXTRA_VERSION=".0-fallback"
+ payload __PAYLOAD__
+end
+
+buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback"
+pci_rom ../../../misc/d945gclf-pci8086,2772.rom vendor_id=0x8086 device_id=0x2772
+