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authorIonela Voinescu <ionela.voinescu@imgtec.com>2015-01-21 01:51:25 +0000
committerPatrick Georgi <pgeorgi@google.com>2015-04-17 09:23:29 +0200
commitdeaaab25365b093229836d4294b1868093df7c47 (patch)
treea1c4171a547d9e53739e9dca7e613fc42060cbc7 /src
parentfb032398d262ff7594c35c65b6f14897bb331a39 (diff)
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arch/mips: Fix bug when performing cache operations
Each type of cache might have different cache line size. Call the proper get_<*>cache_line function for each cache type. Fixes problem with get_L2cache_line which previously targeted L3 cache line in the config register, instead of L2 cache. TODO: add support for tertiary caches and have cache operations be called per CPU, not per architecture. BUG=chrome-os-partner:31438 TEST=tested on Pistachio bring up board; worked as expected; BRANCH=none Change-Id: I7de946cbd6bac716e99fe07cb0deb5aa76c84171 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 62e2803c6f2a3ad02dc88f50a4ae2ea00487e3f4 Original-Change-Id: I03071f24aacac1805cfd89e4f44b14ed1c1e984e Original-Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Original-Reviewed-on: https://chromium-review.googlesource.com/241853 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/9731 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src')
-rw-r--r--src/arch/mips/cache.c22
-rw-r--r--src/arch/mips/include/arch/cache.h2
2 files changed, 20 insertions, 4 deletions
diff --git a/src/arch/mips/cache.c b/src/arch/mips/cache.c
index 209349539..cfdae510b 100644
--- a/src/arch/mips/cache.c
+++ b/src/arch/mips/cache.c
@@ -1,4 +1,3 @@
-
/*
* This file is part of the coreboot project.
*
@@ -20,6 +19,7 @@
#include <arch/cache.h>
#include <symbols.h>
+#include <console/console.h>
/* Cache operations */
@@ -73,12 +73,29 @@
: "i" (op), "R" (*(unsigned char *)(addr))); \
})
+static int get_cache_line(uint8_t type)
+{
+ switch (type) {
+ case ICACHE: return get_icache_line();
+ case DCACHE: return get_dcache_line();
+ case L2CACHE: return get_L2cache_line();
+ default:
+ printk(BIOS_ERR, "%s: Error: unsupported cache type.\n",
+ __func__);
+ return 0;
+ }
+ return 0;
+}
+
void perform_cache_operation(uintptr_t start, size_t size, uint8_t operation)
{
u32 line_size, line_mask;
uintptr_t end;
- line_size = get_icache_line();
+ line_size = get_cache_line((operation >> CACHE_TYPE_SHIFT) &
+ CACHE_TYPE_MASK);
+ if (!line_size)
+ return;
line_mask = ~(line_size-1);
end = (start + (line_size - 1) + size) & line_mask;
start &= line_mask;
@@ -108,5 +125,4 @@ void cache_invalidate_all(uintptr_t start, size_t size)
perform_cache_operation(start, size, CACHE_CODE(ICACHE, WB_INVD));
perform_cache_operation(start, size, CACHE_CODE(DCACHE, WB_INVD));
perform_cache_operation(start, size, CACHE_CODE(L2CACHE, WB_INVD));
-
}
diff --git a/src/arch/mips/include/arch/cache.h b/src/arch/mips/include/arch/cache.h
index 8c7b6f1ae..907505981 100644
--- a/src/arch/mips/include/arch/cache.h
+++ b/src/arch/mips/include/arch/cache.h
@@ -25,7 +25,7 @@
#define get_icache_line() __get_line_size($16, 1, 19, 3)
#define get_dcache_line() __get_line_size($16, 1, 10, 3)
-#define get_L2cache_line() __get_line_size($16, 2, 20, 4)
+#define get_L2cache_line() __get_line_size($16, 2, 4, 4)
#define CACHE_TYPE_SHIFT (0)
#define CACHE_OP_SHIFT (2)