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authorJoseph Lo <josephl@nvidia.com>2015-04-29 17:14:03 +0800
committerPatrick Georgi <pgeorgi@google.com>2015-05-18 13:16:33 +0200
commit589e63ee7c302a96ef7f9349838936dccdb19f52 (patch)
tree6d47a03042cafdbbbce6fdee5139b9ac818131f2 /src
parentb7d0ffd1edb358c089c0fe94711aac65eeb81d6a (diff)
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drivers/gic: reprogram the GIC CPU interface to bypass IRQ
GICv2 provides a wake IRQ/FIQ (for wake-event purpose), which are not disabled by GIC CPU interface. This is done by adding a bypass override capability when the interrupts are disabled at the CPU interface. To support this, there are four bits about IRQ/FIQ BypassDisable in CPU interface Control Register. So the CPU can exit from WFI when an asserted IRQ is coming. This is critical for power gating a CPU. BRANCH=none BUG=chrome-os-partner:39620 TEST=testing with CPU idle with power down state support and CPU can wake up normally Change-Id: I71ac642e28024a562db898665b74a5791fce325a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 3a3f098cbf3fbfdab8150ebd4fd688fdb472b529 Original-Change-Id: I20569a18f34a4b11b8c8c67ea255b3d0f021839f Original-Signed-off-by: Joseph Lo <josephl@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/269116 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/10172 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src')
-rw-r--r--src/drivers/gic/gic.c11
1 files changed, 11 insertions, 0 deletions
diff --git a/src/drivers/gic/gic.c b/src/drivers/gic/gic.c
index 71073a580..b7bce2a37 100644
--- a/src/drivers/gic/gic.c
+++ b/src/drivers/gic/gic.c
@@ -26,6 +26,10 @@
enum {
ENABLE_GRP0 = 0x1 << 0,
ENABLE_GRP1 = 0x1 << 1,
+ FIQ_BYP_DIS_GRP0 = 0x1 << 5,
+ IRQ_BYP_DIS_GRP0 = 0x1 << 6,
+ FIQ_BYP_DIS_GRP1 = 0x1 << 7,
+ IRQ_BYP_DIS_GRP1 = 0x1 << 8,
};
struct gic {
@@ -135,6 +139,13 @@ void gic_disable(void)
/* Disable secure, non-secure interrupts. */
uint32_t val = gic_read(&gicc->ctlr);
val &= ~(ENABLE_GRP0 | ENABLE_GRP1);
+ /*
+ * Enable the IRQ/FIQ BypassDisable bits to bypass the IRQs.
+ * So the CPU can wake up from power gating state when the GIC
+ * was disabled.
+ */
+ val |= FIQ_BYP_DIS_GRP0 | IRQ_BYP_DIS_GRP0 |
+ FIQ_BYP_DIS_GRP1 | IRQ_BYP_DIS_GRP1;
gic_write(&gicc->ctlr, val);
}