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authorScott Duplichan <scott@notabs.org>2011-05-15 22:07:56 +0000
committerMarc Jones <marc.jones@amd.com>2011-05-15 22:07:56 +0000
commita64ab46b629737658a461914d0d63ae713c0e760 (patch)
tree63b05f32b07d0c5759cf04b7c12334dc1d8b7469 /src/southbridge/amd/cimx_wrapper/sb800/late.c
parent769527e523bb40ecb33a1f6811dae0d689ca4e26 (diff)
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Update gpp port configuration.
Signed-off-by: Scott Duplichan <scott@notabs.org> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6592 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/southbridge/amd/cimx_wrapper/sb800/late.c')
-rw-r--r--src/southbridge/amd/cimx_wrapper/sb800/late.c14
1 files changed, 7 insertions, 7 deletions
diff --git a/src/southbridge/amd/cimx_wrapper/sb800/late.c b/src/southbridge/amd/cimx_wrapper/sb800/late.c
index d8816fa1c..c72b2bec8 100644
--- a/src/southbridge/amd/cimx_wrapper/sb800/late.c
+++ b/src/southbridge/amd/cimx_wrapper/sb800/late.c
@@ -315,7 +315,6 @@ static const struct pci_driver PORTD_driver __pci_driver = {
*/
static void sb800_enable(device_t dev)
{
- u8 gpp_port = 0;
struct southbridge_amd_cimx_wrapper_sb800_config *sb_chip =
(struct southbridge_amd_cimx_wrapper_sb800_config *)(dev->chip_info);
@@ -414,15 +413,16 @@ static void sb800_enable(device_t dev)
break;
case (0x15 << 3) | 0: /* 0:15:0 PCIe PortA */
+ sb_config->PORTCONFIG[0].PortCfg.PortPresent = dev->enabled;
+ return;
case (0x15 << 3) | 1: /* 0:15:1 PCIe PortB */
+ sb_config->PORTCONFIG[1].PortCfg.PortPresent = dev->enabled;
+ return;
case (0x15 << 3) | 2: /* 0:15:2 PCIe PortC */
+ sb_config->PORTCONFIG[2].PortCfg.PortPresent = dev->enabled;
+ return;
case (0x15 << 3) | 3: /* 0:15:3 PCIe PortD */
- gpp_port = (dev->path.pci.devfn) & 0x03;
- if (dev->enabled) {
- sb_config->PORTCONFIG[gpp_port].PortCfg.PortPresent = ENABLED;
- } else {
- sb_config->PORTCONFIG[gpp_port].PortCfg.PortPresent = DISABLED;
- }
+ sb_config->PORTCONFIG[3].PortCfg.PortPresent = dev->enabled;
/*
* GPP_CFGMODE_X4000: PortA Lanes[3:0]