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authorScott Duplichan <scott@notabs.org>2011-06-18 10:46:45 -0500
committerCristian Măgherușan-Stanciu <cristi.magherusan@gmail.com>2011-06-19 02:50:32 +0200
commit8fed77ae4c46122859d0718678e54546e126d4bc (patch)
tree67a67eed2ead6e6833e17096a213a0f20005ede5 /src/southbridge/amd/cimx_wrapper/sb800/late.c
parent47b3fb403d5b7f7fc756d3567bacf66ea0c1b9e9 (diff)
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ASRock E350M1: Configure SB800 GPP ports to support onboard pcie nic
Scott Duplichan's patch from the mailing list: sb800 cimx wrapper: Run the complete sb800 cimx sbBeforePciInit() function once, after determining device 0x15 function enables. 1) Update the asrock e350m1 devicetree.cb to match the hardware. 2) Change the way the sb800 cimx wrapper code works. The original cimx code calls sb800 cimx function sbBeforePciInit() once. When ported to coreboot, the gpp component of this function was called once for each gpp port, as the gpp port's enable/disable state became known. A 05/15/2011 change makes the early gpp code run only once, triggered by processing the 4th gpp port. This method is not general enough because the 4th gpp port is not enabled on all boards. With the current change, the early gpp code runs when the first gpp port is processed. If any gpp ports are enabled, the first must be enabled. Tested with Win7 and linux on asrock e350m1. This change will also affect amd inagua, and has not been tested on that board. Change-Id: I93d44c216bfcab3c3a8fbb79d23dab43a65850e6 Signed-off-by: Scott Duplichan <scott@notabs.org> Acked-by: Marshall Buschman <mbuschman@lucidmachines.com> Reviewed-on: http://review.coreboot.org/44 Tested-by: build bot (Jenkins) Reviewed-by: Cristian Măgherușan-Stanciu <cristi.magherusan@gmail.com>
Diffstat (limited to 'src/southbridge/amd/cimx_wrapper/sb800/late.c')
-rw-r--r--src/southbridge/amd/cimx_wrapper/sb800/late.c31
1 files changed, 11 insertions, 20 deletions
diff --git a/src/southbridge/amd/cimx_wrapper/sb800/late.c b/src/southbridge/amd/cimx_wrapper/sb800/late.c
index 50eeb48e8..692644357 100644
--- a/src/southbridge/amd/cimx_wrapper/sb800/late.c
+++ b/src/southbridge/amd/cimx_wrapper/sb800/late.c
@@ -413,16 +413,13 @@ static void sb800_enable(device_t dev)
break;
case (0x15 << 3) | 0: /* 0:15:0 PCIe PortA */
- sb_config->PORTCONFIG[0].PortCfg.PortPresent = dev->enabled;
- return;
- case (0x15 << 3) | 1: /* 0:15:1 PCIe PortB */
- sb_config->PORTCONFIG[1].PortCfg.PortPresent = dev->enabled;
- return;
- case (0x15 << 3) | 2: /* 0:15:2 PCIe PortC */
- sb_config->PORTCONFIG[2].PortCfg.PortPresent = dev->enabled;
- return;
- case (0x15 << 3) | 3: /* 0:15:3 PCIe PortD */
- sb_config->PORTCONFIG[3].PortCfg.PortPresent = dev->enabled;
+ {
+ device_t device;
+ for (device = dev; device; device = device->next) {
+ if (dev->path.type != DEVICE_PATH_PCI) continue;
+ if ((device->path.pci.devfn & ~7) != PCI_DEVFN(0x15,0)) break;
+ sb_config->PORTCONFIG[device->path.pci.devfn & 3].PortCfg.PortPresent = device->enabled;
+ }
/*
* GPP_CFGMODE_X4000: PortA Lanes[3:0]
@@ -430,22 +427,16 @@ static void sb800_enable(device_t dev)
* GPP_CFGMODE_X2110: PortA Lanes[1:0], PortB Lane2, PortC Lane3
* GPP_CFGMODE_X1111: PortA Lanes0, PortB Lane1, PortC Lane2, PortD Lane3
*/
- if (sb_config->GppLinkConfig != sb_chip->gpp_configuration) {
- sb_config->GppLinkConfig = sb_chip->gpp_configuration;
- }
-
- sbPcieGppEarlyInit(sb_config);
+ sb_config->GppLinkConfig = sb_chip->gpp_configuration;
+ sb_config->StdHeader.Func = SB_BEFORE_PCI_INIT;
+ AmdSbDispatcher(sb_config);
break;
+ }
default:
break;
}
- /* Special setting ABCFG registers before PCI emulation. */
- abSpecialSetBeforePciEnum(sb_config);
- usbDesertPll(sb_config);
- //sb_config->StdHeader.Func = SB_BEFORE_PCI_INIT;
- //AmdSbDispatcher(sb_config);
}
struct chip_operations southbridge_amd_cimx_wrapper_sb800_ops = {