aboutsummaryrefslogtreecommitdiffstats
path: root/src/southbridge/amd/cimx_wrapper/sb800/late.c
diff options
context:
space:
mode:
authorKerry She <kerry.she@amd.com>2011-06-01 02:00:30 +0000
committerKerry She <Kerry.She@amd.com>2011-06-01 02:00:30 +0000
commit76d53b22d393ca15d3c0eef8b2d37478000ae86c (patch)
tree1b133aea681110865af869a31d8cd915fc8dae21 /src/southbridge/amd/cimx_wrapper/sb800/late.c
parent991f8808933a8b528108dcd48a029ebf40b05c6b (diff)
downloadcoreboot-76d53b22d393ca15d3c0eef8b2d37478000ae86c.tar.gz
coreboot-76d53b22d393ca15d3c0eef8b2d37478000ae86c.tar.xz
coreboot-76d53b22d393ca15d3c0eef8b2d37478000ae86c.zip
trivial remove blanks at the end of line
Signed-off-by: Kerry She <kerry.she@amd.com> Acked-by: Kerry She <kerry.she@amd.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6614 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/southbridge/amd/cimx_wrapper/sb800/late.c')
-rw-r--r--src/southbridge/amd/cimx_wrapper/sb800/late.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/southbridge/amd/cimx_wrapper/sb800/late.c b/src/southbridge/amd/cimx_wrapper/sb800/late.c
index de1637a0c..50eeb48e8 100644
--- a/src/southbridge/amd/cimx_wrapper/sb800/late.c
+++ b/src/southbridge/amd/cimx_wrapper/sb800/late.c
@@ -27,7 +27,7 @@
#include "lpc.h" /* lpc_read_resources */
#include "SBPLATFORM.h" /* Platfrom Specific Definitions */
#include "cfg.h" /* sb800 Cimx configuration */
-#include "chip.h" /* struct southbridge_amd_cimx_wrapper_sb800_config */
+#include "chip.h" /* struct southbridge_amd_cimx_wrapper_sb800_config */
/*implement in mainboard.c*/
@@ -363,7 +363,7 @@ static void sb800_enable(device_t dev)
/* Assign the ioapic ID the next available number after the processor core local APIC IDs */
setup_ioapic(ioapic_base, CONFIG_MAX_CPUS * CONFIG_MAX_PHYSICAL_CPUS);
#elif (CONFIG_APIC_ID_OFFSET > 0)
- /* Assign the ioapic ID the value 0. Processor APIC IDs follow. */
+ /* Assign the ioapic ID the value 0. Processor APIC IDs follow. */
setup_ioapic(ioapic_base, 0);
#else
#error "The processor APIC IDs must be lifted to make room for the I/O APIC ID"