path: root/src/soc/samsung/exynos5250/Makefile.inc
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authorHung-Te Lin <hungte@chromium.org>2013-09-27 12:45:45 +0800
committerIsaac Christensen <isaac.christensen@se-eng.com>2014-08-26 17:55:18 +0200
commit22d0ca0ceb802675cdcab1472b8477066f729373 (patch)
tree79e2e38a2c6b34125f48b05cfd7f9ef3c88c833d /src/soc/samsung/exynos5250/Makefile.inc
parentb123e0d3345554d7e93361bb4511a53bc95d41a1 (diff)
armv7: Move Exynos from 'cpu' to 'soc'.
The Exynos family and most ARM products are SoC, not just CPU. We used to put ARM code in src/cpu to avoid polluting the code base for what was essentially an experiment at the time. Now that it's past the experimental phase and we're going to see more SoCs (including intel/baytrail) in coreboot. Change-Id: I5ea1f822664244edf5f77087bc8018d7c535f81c Reviewed-on: https://chromium-review.googlesource.com/170891 Tested-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Ronald Minnich <rminnich@chromium.org> Commit-Queue: Hung-Te Lin <hungte@chromium.org> (cherry picked from commit c8bb8fe0b20be37465f93c738d80e7e43033670a) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6739 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/soc/samsung/exynos5250/Makefile.inc')
1 files changed, 62 insertions, 0 deletions
diff --git a/src/soc/samsung/exynos5250/Makefile.inc b/src/soc/samsung/exynos5250/Makefile.inc
new file mode 100644
index 000000000..a15bc9c6a
--- /dev/null
+++ b/src/soc/samsung/exynos5250/Makefile.inc
@@ -0,0 +1,62 @@
+bootblock-y += spi.c alternate_cbfs.c
+bootblock-y += bootblock.c
+bootblock-y += pinmux.c mct.c power.c
+# Clock is required for UART
+bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += clock_init.c
+bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += clock.c
+bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += monotonic_timer.c
+bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += uart.c
+bootblock-y += wakeup.c
+bootblock-y += gpio.c
+bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += timer.c
+romstage-y += spi.c alternate_cbfs.c
+romstage-y += clock.c
+romstage-y += clock_init.c
+romstage-y += pinmux.c # required by s3c24x0_i2c and uart.
+romstage-y += dmc_common.c
+romstage-y += dmc_init_ddr3.c
+romstage-y += power.c
+romstage-y += mct.c
+romstage-y += monotonic_timer.c
+romstage-y += uart.c
+romstage-y += wakeup.c
+romstage-y += gpio.c
+romstage-y += timer.c
+romstage-y += trustzone.c
+romstage-y += i2c.c
+#romstage-y += wdt.c
+romstage-y += cbmem.c
+ramstage-y += spi.c alternate_cbfs.c
+ramstage-y += clock.c
+ramstage-y += clock_init.c
+ramstage-y += pinmux.c
+ramstage-y += power.c
+ramstage-$(CONFIG_DRIVERS_UART) += uart.c
+ramstage-y += cpu.c
+ramstage-y += tmu.c
+ramstage-y += mct.c
+ramstage-y += monotonic_timer.c
+ramstage-y += timer.c
+ramstage-y += gpio.c
+ramstage-y += i2c.c
+ramstage-y += dp-reg.c
+ramstage-y += fb.c
+ramstage-y += usb.c
+ramstage-y += cbmem.c
+# Run an intermediate step when producing coreboot.rom
+# that adds additional components to the final firmware
+# image outside of CBFS
+.PHONY: exynos5250_add_bl1
+$(obj)/coreboot.rom: exynos5250_add_bl1
+exynos5250_add_bl1: $(obj)/coreboot.pre
+ printf " DD Adding Samsung Exynos5250 BL1\n"
+ # TODO(hungte) Change this 'cpu' to soc when build scripts are changed.
+ dd if=3rdparty/cpu/samsung/exynos5250/bl1.bin \
+ of=$(obj)/coreboot.pre conv=notrunc >/dev/null 2>&1