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authorKevin Paul Herbert <kph@meraki.net>2014-12-24 18:43:20 -0800
committerAlexandru Gagniuc <mr.nuke.me@gmail.com>2015-02-15 08:50:22 +0100
commitbde6d309dfafe58732ec46314a2d4c08974b62d4 (patch)
tree17ba00565487ddfbb5759c96adfbb3fffe2a4550 /src/northbridge
parent4b10dec1a66122b515b2191f823d7fd379ec655f (diff)
downloadcoreboot-bde6d309dfafe58732ec46314a2d4c08974b62d4.tar.gz
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x86: Change MMIO addr in readN(addr)/writeN(addr, val) to pointer
On x86, change the type of the address parameter in read8()/read16/read32()/write8()/write16()/write32() to be a pointer, instead of unsigned long. Change-Id: Ic26dd8a72d82828b69be3c04944710681b7bd330 Signed-off-by: Kevin Paul Herbert <kph@meraki.net> Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/7784 Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/northbridge')
-rw-r--r--src/northbridge/amd/cimx/rd890/late.c4
-rw-r--r--src/northbridge/intel/e7501/raminit.c11
-rw-r--r--src/northbridge/intel/e7505/raminit.c10
-rw-r--r--src/northbridge/intel/fsp_sandybridge/acpi.c2
-rw-r--r--src/northbridge/intel/fsp_sandybridge/early_init.c8
-rw-r--r--src/northbridge/intel/fsp_sandybridge/northbridge.h7
-rw-r--r--src/northbridge/intel/gm45/early_init.c4
-rw-r--r--src/northbridge/intel/gm45/gm45.h7
-rw-r--r--src/northbridge/intel/gm45/gma.c10
-rw-r--r--src/northbridge/intel/gm45/pcie.c6
-rw-r--r--src/northbridge/intel/gm45/raminit.c12
-rw-r--r--src/northbridge/intel/gm45/raminit_read_write_training.c12
-rw-r--r--src/northbridge/intel/gm45/raminit_receive_enable_calibration.c2
-rw-r--r--src/northbridge/intel/haswell/acpi.c2
-rw-r--r--src/northbridge/intel/haswell/early_init.c4
-rw-r--r--src/northbridge/intel/haswell/gma.c4
-rw-r--r--src/northbridge/intel/haswell/haswell.h4
-rw-r--r--src/northbridge/intel/haswell/minihd.c7
-rw-r--r--src/northbridge/intel/i3100/i3100.h2
-rw-r--r--src/northbridge/intel/i3100/raminit.c9
-rw-r--r--src/northbridge/intel/i3100/raminit_ep80579.c4
-rw-r--r--src/northbridge/intel/i440bx/raminit.c5
-rw-r--r--src/northbridge/intel/i5000/raminit.h2
-rw-r--r--src/northbridge/intel/i82810/raminit.c10
-rw-r--r--src/northbridge/intel/i82830/raminit.c8
-rw-r--r--src/northbridge/intel/i82830/smihandler.c2
-rw-r--r--src/northbridge/intel/i855/raminit.c2
-rw-r--r--src/northbridge/intel/i945/early_init.c12
-rw-r--r--src/northbridge/intel/i945/i945.h5
-rw-r--r--src/northbridge/intel/i945/raminit.c2
-rw-r--r--src/northbridge/intel/i945/rcven.c4
-rw-r--r--src/northbridge/intel/nehalem/acpi.c2
-rw-r--r--src/northbridge/intel/nehalem/early_init.c12
-rw-r--r--src/northbridge/intel/nehalem/gma.c14
-rw-r--r--src/northbridge/intel/nehalem/nehalem.h9
-rw-r--r--src/northbridge/intel/nehalem/raminit.c158
-rw-r--r--src/northbridge/intel/sandybridge/acpi.c2
-rw-r--r--src/northbridge/intel/sandybridge/early_init.c10
-rw-r--r--src/northbridge/intel/sandybridge/gma.c9
-rw-r--r--src/northbridge/intel/sandybridge/gma.h2
-rw-r--r--src/northbridge/intel/sandybridge/gma_ivybridge_lvds.c8
-rw-r--r--src/northbridge/intel/sandybridge/gma_sandybridge_lvds.c6
-rw-r--r--src/northbridge/intel/sandybridge/raminit_native.c128
-rw-r--r--src/northbridge/intel/sandybridge/sandybridge.h7
-rw-r--r--src/northbridge/intel/sch/early_init.c3
-rw-r--r--src/northbridge/intel/sch/sch.h2
-rw-r--r--src/northbridge/via/cn700/raminit.c8
-rw-r--r--src/northbridge/via/cx700/lpc.c2
-rw-r--r--src/northbridge/via/cx700/raminit.c152
-rw-r--r--src/northbridge/via/vx900/lpc.c6
-rw-r--r--src/northbridge/via/vx900/traf_ctrl.c12
51 files changed, 390 insertions, 345 deletions
diff --git a/src/northbridge/amd/cimx/rd890/late.c b/src/northbridge/amd/cimx/rd890/late.c
index fa23344ef..9a73e63f8 100644
--- a/src/northbridge/amd/cimx/rd890/late.c
+++ b/src/northbridge/amd/cimx/rd890/late.c
@@ -119,10 +119,10 @@ struct chip_operations northbridge_amd_cimx_rd890_ops = {
static void ioapic_init(struct device *dev)
{
- u32 ioapic_base;
+ void *ioapic_base;
pci_write_config32(dev, 0xF8, 0x1);
- ioapic_base = pci_read_config32(dev, 0xFC) & 0xfffffff0;
+ ioapic_base = (void *)(pci_read_config32(dev, 0xFC) & 0xfffffff0);
clear_ioapic(ioapic_base);
setup_ioapic(ioapic_base, 1);
}
diff --git a/src/northbridge/intel/e7501/raminit.c b/src/northbridge/intel/e7501/raminit.c
index 22d1bbc7a..f4fc9a8a7 100644
--- a/src/northbridge/intel/e7501/raminit.c
+++ b/src/northbridge/intel/e7501/raminit.c
@@ -44,7 +44,7 @@ Definitions:
// NOTE: This used to be 0x100000.
// That doesn't work on systems where A20M# is asserted, because
// attempts to access 0x1000NN end up accessing 0x0000NN.
-#define RCOMP_MMIO 0x200000
+#define RCOMP_MMIO ((u8 *)0x200000)
struct dimm_size {
unsigned long side1;
@@ -893,8 +893,8 @@ static void do_ram_command(uint8_t command, uint16_t jedec_mode_bits)
// NOTE: 2^26 == 64 MB
- uint32_t dimm_start_address =
- dimm_start_64M_multiple << 26;
+ u8 *dimm_start_address = (u8 *)
+ (dimm_start_64M_multiple << 26);
RAM_DEBUG_MESSAGE(" Sending RAM command to 0x");
RAM_DEBUG_HEX32(dimm_start_address + e7501_mode_bits);
@@ -1704,7 +1704,7 @@ static void ram_set_d0f0_regs(void)
* @param src_addr TODO
* @param dst_addr TODO
*/
-static void write_8dwords(const uint32_t *src_addr, uint32_t dst_addr)
+static void write_8dwords(const uint32_t *src_addr, u8 *dst_addr)
{
int i;
for (i = 0; i < 8; i++) {
@@ -1737,7 +1737,8 @@ static void ram_set_rcomp_regs(void)
pci_write_config32(PCI_DEV(0, 0, 0), MAYBE_MCHTST, dword);
// Set the RCOMP MMIO base address
- pci_write_config32(PCI_DEV(0, 0, 0), MAYBE_SMRBASE, RCOMP_MMIO);
+ pci_write_config32(PCI_DEV(0, 0, 0), MAYBE_SMRBASE,
+ (uintptr_t)RCOMP_MMIO);
// Block RCOMP updates while we configure the registers
dword = read32(RCOMP_MMIO + MAYBE_SMRCTL);
diff --git a/src/northbridge/intel/e7505/raminit.c b/src/northbridge/intel/e7505/raminit.c
index b758c610f..fc715bc1d 100644
--- a/src/northbridge/intel/e7505/raminit.c
+++ b/src/northbridge/intel/e7505/raminit.c
@@ -63,7 +63,7 @@ Definitions:
// NOTE: This used to be 0x100000.
// That doesn't work on systems where A20M# is asserted, because
// attempts to access 0x1000NN end up accessing 0x0000NN.
-#define RCOMP_MMIO 0x200000
+#define RCOMP_MMIO ((u8 *)0x200000)
struct dimm_size {
unsigned long side1;
@@ -665,7 +665,7 @@ SDRAM configuration functions:
static void do_ram_command(uint8_t command, uint16_t jedec_mode_bits)
{
uint8_t dimm_start_64M_multiple;
- uint32_t dimm_start_address;
+ uintptr_t dimm_start_address;
uint32_t dram_controller_mode;
uint8_t i;
@@ -713,7 +713,7 @@ static void do_ram_command(uint8_t command, uint16_t jedec_mode_bits)
if (dimm_end_64M_multiple > dimm_start_64M_multiple) {
dimm_start_address &= 0x3ffffff;
dimm_start_address |= dimm_start_64M_multiple << 26;
- read32(dimm_start_address);
+ read32((void *)dimm_start_address);
// Set the start of the next DIMM
dimm_start_64M_multiple = dimm_end_64M_multiple;
}
@@ -1521,7 +1521,7 @@ static void RAM_RESET_DDR_PTR(void)
* @param src_addr TODO
* @param dst_addr TODO
*/
-static void write_8dwords(const uint32_t *src_addr, uint32_t dst_addr)
+static void write_8dwords(const uint32_t *src_addr, u8 *dst_addr)
{
int i;
for (i = 0; i < 8; i++) {
@@ -1627,7 +1627,7 @@ static void ram_set_rcomp_regs(void)
{
/* Set the RCOMP MMIO base address */
mchtest_control(RCOMP_BAR_ENABLE);
- pci_write_config32(MCHDEV, SMRBASE, RCOMP_MMIO);
+ pci_write_config32(MCHDEV, SMRBASE, (uintptr_t)RCOMP_MMIO);
/* Block RCOMP updates while we configure the registers */
rcomp_smr_control(RCOMP_HOLD);
diff --git a/src/northbridge/intel/fsp_sandybridge/acpi.c b/src/northbridge/intel/fsp_sandybridge/acpi.c
index a372e7b70..bf23e65d1 100644
--- a/src/northbridge/intel/fsp_sandybridge/acpi.c
+++ b/src/northbridge/intel/fsp_sandybridge/acpi.c
@@ -120,7 +120,7 @@ static int init_opregion_vbt(igd_opregion_t *opregion)
optionrom_vbt_t *vbt = (optionrom_vbt_t *)(vbios +
oprom->vbt_offset);
- if (read32((unsigned long)vbt->hdr_signature) != VBT_SIGNATURE) {
+ if (read32(vbt->hdr_signature) != VBT_SIGNATURE) {
printk(BIOS_DEBUG, "VBT not found!\n");
return 1;
}
diff --git a/src/northbridge/intel/fsp_sandybridge/early_init.c b/src/northbridge/intel/fsp_sandybridge/early_init.c
index 4b615e9dc..f86690dc0 100644
--- a/src/northbridge/intel/fsp_sandybridge/early_init.c
+++ b/src/northbridge/intel/fsp_sandybridge/early_init.c
@@ -32,12 +32,12 @@ static void sandybridge_setup_bars(void)
/* Set up all hardcoded northbridge BARs */
pci_write_config32(PCI_DEV(0, 0x00, 0), EPBAR, DEFAULT_EPBAR | 1);
pci_write_config32(PCI_DEV(0, 0x00, 0), EPBAR + 4, (0LL+DEFAULT_EPBAR) >> 32);
- pci_write_config32(PCI_DEV(0, 0x00, 0), MCHBAR, DEFAULT_MCHBAR | 1);
- pci_write_config32(PCI_DEV(0, 0x00, 0), MCHBAR + 4, (0LL+DEFAULT_MCHBAR) >> 32);
+ pci_write_config32(PCI_DEV(0, 0x00, 0), MCHBAR, (uintptr_t)DEFAULT_MCHBAR | 1);
+ pci_write_config32(PCI_DEV(0, 0x00, 0), MCHBAR + 4, (0LL+(uintptr_t)DEFAULT_MCHBAR) >> 32);
pci_write_config32(PCI_DEV(0, 0x00, 0), PCIEXBAR, DEFAULT_PCIEXBAR | 5); /* 64MB - busses 0-63 */
pci_write_config32(PCI_DEV(0, 0x00, 0), PCIEXBAR + 4, (0LL+DEFAULT_PCIEXBAR) >> 32);
- pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR, DEFAULT_DMIBAR | 1);
- pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR + 4, (0LL+DEFAULT_DMIBAR) >> 32);
+ pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR, (uintptr_t)DEFAULT_DMIBAR | 1);
+ pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR + 4, (0LL+(uintptr_t)DEFAULT_DMIBAR) >> 32);
/* Set C0000-FFFFF to access RAM on both reads and writes */
pci_write_config8(PCI_DEV(0, 0x00, 0), PAM0, 0x30);
diff --git a/src/northbridge/intel/fsp_sandybridge/northbridge.h b/src/northbridge/intel/fsp_sandybridge/northbridge.h
index d67d696d9..0432963ba 100644
--- a/src/northbridge/intel/fsp_sandybridge/northbridge.h
+++ b/src/northbridge/intel/fsp_sandybridge/northbridge.h
@@ -49,10 +49,15 @@
/* Northbridge BARs */
#define DEFAULT_PCIEXBAR CONFIG_MMCONF_BASE_ADDRESS /* 4 KB per PCIe device */
+#ifndef __ACPI__
+#define DEFAULT_MCHBAR ((u8 *)0xfed10000) /* 16 KB */
+#define DEFAULT_DMIBAR ((u8 *)0xfed18000) /* 4 KB */
+#else
#define DEFAULT_MCHBAR 0xfed10000 /* 16 KB */
#define DEFAULT_DMIBAR 0xfed18000 /* 4 KB */
+#endif
#define DEFAULT_EPBAR 0xfed19000 /* 4 KB */
-#define DEFAULT_RCBABASE 0xfed1c000
+#define DEFAULT_RCBABASE ((u8 *)0xfed1c000)
#if CONFIG_SOUTHBRIDGE_INTEL_FSP_BD82X6X
#include <southbridge/intel/fsp_bd82x6x/pch.h>
diff --git a/src/northbridge/intel/gm45/early_init.c b/src/northbridge/intel/gm45/early_init.c
index 335ef6874..224dfcefe 100644
--- a/src/northbridge/intel/gm45/early_init.c
+++ b/src/northbridge/intel/gm45/early_init.c
@@ -26,10 +26,10 @@ void gm45_early_init(void)
const device_t d0f0 = PCI_DEV(0, 0, 0);
/* Setup MCHBAR. */
- pci_write_config32(d0f0, D0F0_MCHBAR_LO, DEFAULT_MCHBAR | 1);
+ pci_write_config32(d0f0, D0F0_MCHBAR_LO, (uintptr_t)DEFAULT_MCHBAR | 1);
/* Setup DMIBAR. */
- pci_write_config32(d0f0, D0F0_DMIBAR_LO, DEFAULT_DMIBAR | 1);
+ pci_write_config32(d0f0, D0F0_DMIBAR_LO, (uintptr_t)DEFAULT_DMIBAR | 1);
/* Setup EPBAR. */
pci_write_config32(d0f0, D0F0_EPBAR_LO, DEFAULT_EPBAR | 1);
diff --git a/src/northbridge/intel/gm45/gm45.h b/src/northbridge/intel/gm45/gm45.h
index 5bdf9e464..a31ea7da4 100644
--- a/src/northbridge/intel/gm45/gm45.h
+++ b/src/northbridge/intel/gm45/gm45.h
@@ -187,10 +187,15 @@ enum {
(could be reduced to 10 bytes) */
+#ifndef __ACPI__
+#define DEFAULT_MCHBAR ((u8 *)0xfed14000)
+#define DEFAULT_DMIBAR ((u8 *)0xfed18000)
+#else
#define DEFAULT_MCHBAR 0xfed14000
#define DEFAULT_DMIBAR 0xfed18000
+#endif
#define DEFAULT_EPBAR 0xfed19000
-#define DEFAULT_HECIBAR 0xfed1a000
+#define DEFAULT_HECIBAR ((u8 *)0xfed1a000)
/* 4 KB per PCIe device */
#define DEFAULT_PCIEXBAR CONFIG_MMCONF_BASE_ADDRESS
diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c
index 74e16ad2f..4cf277616 100644
--- a/src/northbridge/intel/gm45/gma.c
+++ b/src/northbridge/intel/gm45/gma.c
@@ -43,12 +43,12 @@ static struct resource *gtt_res = NULL;
void gtt_write(u32 reg, u32 data)
{
- write32(gtt_res->base + reg, data);
+ write32(res2mmio(gtt_res, reg, 0), data);
}
#if IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT)
-static void power_port(u32 mmio)
+static void power_port(u8 *mmio)
{
read32(mmio + 0x00061100); // = 0x00000000
write32(mmio + 0x00061100, 0x00000000);
@@ -103,7 +103,7 @@ static void power_port(u32 mmio)
}
static void intel_gma_init(const struct northbridge_intel_gm45_config *info,
- u32 mmio, u32 physbase, u16 piobase, u32 lfb)
+ u8 *mmio, u32 physbase, u16 piobase, u32 lfb)
{
int i;
@@ -464,8 +464,8 @@ static void gma_func0_init(struct device *dev)
&& lfb_res && lfb_res->base) {
printk(BIOS_SPEW, "Initializing VGA without OPROM. MMIO 0x%llx\n",
gtt_res->base);
- intel_gma_init(conf, gtt_res->base, physbase, pio_res->base,
- lfb_res->base);
+ intel_gma_init(conf, res2mmio(gtt_res, 0, 0), physbase,
+ pio_res->base, lfb_res->base);
}
/* Linux relies on VBT for panel info. */
diff --git a/src/northbridge/intel/gm45/pcie.c b/src/northbridge/intel/gm45/pcie.c
index 39791a62b..ae34a11b5 100644
--- a/src/northbridge/intel/gm45/pcie.c
+++ b/src/northbridge/intel/gm45/pcie.c
@@ -308,7 +308,7 @@ static void setup_rcrb(const int peg_enabled)
/* Link1: component ID 1, link valid. */
EPBAR32(EPLE1D) = (EPBAR32(EPLE1D) & 0xff000000) | (1 << 16) | (1 << 0);
- EPBAR32(EPLE1A) = DEFAULT_DMIBAR;
+ EPBAR32(EPLE1A) = (uintptr_t)DEFAULT_DMIBAR;
if (peg_enabled)
/* Link2: link_valid. */
@@ -322,12 +322,12 @@ static void setup_rcrb(const int peg_enabled)
/* Link1: target port 0, component id 2 (ICH), link valid. */
DMIBAR32(DMILE1D) = (0 << 24) | (2 << 16) | (1 << 0);
- DMIBAR32(DMILE1A) = DEFAULT_RCBA;
+ DMIBAR32(DMILE1A) = (uintptr_t)DEFAULT_RCBA;
/* Link2: component ID 1 (MCH), link valid */
DMIBAR32(DMILE2D) =
(DMIBAR32(DMILE2D) & 0xff000000) | (1 << 16) | (1 << 0);
- DMIBAR32(DMILE2A) = DEFAULT_MCHBAR;
+ DMIBAR32(DMILE2A) = (uintptr_t)DEFAULT_MCHBAR;
}
void gm45_late_init(const stepping_t stepping)
diff --git a/src/northbridge/intel/gm45/raminit.c b/src/northbridge/intel/gm45/raminit.c
index 60b05bdcb..2c810de81 100644
--- a/src/northbridge/intel/gm45/raminit.c
+++ b/src/northbridge/intel/gm45/raminit.c
@@ -1579,15 +1579,15 @@ static void jedec_init(const timings_t *const timings,
const u32 rankaddr = raminit_get_rank_addr(ch, r);
printk(BIOS_DEBUG, "Performing Jedec initialization at address 0x%08x.\n", rankaddr);
MCHBAR32(DCC_MCHBAR) = (MCHBAR32(DCC_MCHBAR) & ~DCC_SET_EREG_MASK) | DCC_SET_EREGx(2);
- read32(rankaddr | WL);
+ read32((u32 *)(rankaddr | WL));
MCHBAR32(DCC_MCHBAR) = (MCHBAR32(DCC_MCHBAR) & ~DCC_SET_EREG_MASK) | DCC_SET_EREGx(3);
- read32(rankaddr);
+ read32((u32 *)rankaddr);
MCHBAR32(DCC_MCHBAR) = (MCHBAR32(DCC_MCHBAR) & ~DCC_SET_EREG_MASK) | DCC_SET_EREGx(1);
- read32(rankaddr | ODT_120OHMS | ODS_34OHMS);
+ read32((u32 *)(rankaddr | ODT_120OHMS | ODS_34OHMS));
MCHBAR32(DCC_MCHBAR) = (MCHBAR32(DCC_MCHBAR) & ~DCC_CMD_MASK) | DCC_SET_MREG;
- read32(rankaddr | WR | DLL1 | CAS | INTERLEAVED);
+ read32((u32 *)(rankaddr | WR | DLL1 | CAS | INTERLEAVED));
MCHBAR32(DCC_MCHBAR) = (MCHBAR32(DCC_MCHBAR) & ~DCC_CMD_MASK) | DCC_SET_MREG;
- read32(rankaddr | WR | CAS | INTERLEAVED);
+ read32((u32 *)(rankaddr | WR | CAS | INTERLEAVED));
}
}
@@ -1701,7 +1701,7 @@ void raminit(sysinfo_t *const sysinfo, const int s3resume)
/* Wait for some bit, maybe TXT clear. */
if (sysinfo->txt_enabled) {
- while (!(read8(0xfed40000) & (1 << 7))) {}
+ while (!(read8((u8 *)0xfed40000) & (1 << 7))) {}
}
/* Enable SMBUS. */
diff --git a/src/northbridge/intel/gm45/raminit_read_write_training.c b/src/northbridge/intel/gm45/raminit_read_write_training.c
index 5149c2b11..b03cb33c7 100644
--- a/src/northbridge/intel/gm45/raminit_read_write_training.c
+++ b/src/northbridge/intel/gm45/raminit_read_write_training.c
@@ -114,7 +114,7 @@ static int read_training_test(const int channel, const int lane,
for (i = 0; i < addresses->count; ++i) {
unsigned int offset;
for (offset = lane_offset; offset < 320; offset += 8) {
- const u32 read = read32(addresses->addr[i] + offset);
+ const u32 read = read32((u32 *)(addresses->addr[i] + offset));
const u32 good = read_training_schedule[offset >> 3];
if ((read & lane_mask) != (good & lane_mask))
return 0;
@@ -228,7 +228,7 @@ static void perform_read_training(const dimminfo_t *const dimms)
/* Write test pattern. */
unsigned int offset;
for (offset = 0; offset < 320; offset += 4)
- write32(addresses.addr[i] + offset,
+ write32((u32 *)(addresses.addr[i] + offset),
read_training_schedule[offset >> 3]);
}
@@ -436,18 +436,18 @@ static int write_training_test(const address_bunch_t *const addresses,
unsigned int off;
for (off = 0; off < 640; off += 8) {
const u32 pattern = write_training_schedule[off >> 3];
- write32(addr + off, pattern);
- write32(addr + off + 4, pattern);
+ write32((u32 *)(addr + off), pattern);
+ write32((u32 *)(addr + off + 4), pattern);
}
MCHBAR8(0x78) |= 1;
for (off = 0; off < 640; off += 8) {
const u32 good = write_training_schedule[off >> 3];
- const u32 read1 = read32(addr + off);
+ const u32 read1 = read32((u32 *)(addr + off));
if ((read1 & masks[0]) != (good & masks[0]))
goto _bad_timing_out;
- const u32 read2 = read32(addr + off + 4);
+ const u32 read2 = read32((u32 *)(addr + off + 4));
if ((read2 & masks[1]) != (good & masks[1]))
goto _bad_timing_out;
}
diff --git a/src/northbridge/intel/gm45/raminit_receive_enable_calibration.c b/src/northbridge/intel/gm45/raminit_receive_enable_calibration.c
index 5130b599f..62be05e8c 100644
--- a/src/northbridge/intel/gm45/raminit_receive_enable_calibration.c
+++ b/src/northbridge/intel/gm45/raminit_receive_enable_calibration.c
@@ -147,7 +147,7 @@ static int read_dqs_level(const int channel, const int lane)
MCHBAR32(mchbar) |= (1 << 9);
/* Read from this channel. */
- read32(raminit_get_rank_addr(channel, 0));
+ read32((u32 *)raminit_get_rank_addr(channel, 0));
mchbar = 0x14b0 + (channel * 0x0100) + ((7 - lane) * 4);
return MCHBAR32(mchbar) & (1 << 30);
diff --git a/src/northbridge/intel/haswell/acpi.c b/src/northbridge/intel/haswell/acpi.c
index 488170d74..1b77b645d 100644
--- a/src/northbridge/intel/haswell/acpi.c
+++ b/src/northbridge/intel/haswell/acpi.c
@@ -118,7 +118,7 @@ static int init_opregion_vbt(igd_opregion_t *opregion)
optionrom_vbt_t *vbt = (optionrom_vbt_t *)(vbios +
oprom->vbt_offset);
- if (read32((unsigned long)vbt->hdr_signature) != VBT_SIGNATURE) {
+ if (read32(vbt->hdr_signature) != VBT_SIGNATURE) {
printk(BIOS_DEBUG, "VBT not found!\n");
return 1;
}
diff --git a/src/northbridge/intel/haswell/early_init.c b/src/northbridge/intel/haswell/early_init.c
index 7f9f1876b..ef1998401 100644
--- a/src/northbridge/intel/haswell/early_init.c
+++ b/src/northbridge/intel/haswell/early_init.c
@@ -34,8 +34,8 @@ static void haswell_setup_bars(void)
pci_write_config32(PCI_DEV(0, 0x00, 0), EPBAR + 4, (0LL+DEFAULT_EPBAR) >> 32);
pci_write_config32(PCI_DEV(0, 0x00, 0), MCHBAR, DEFAULT_MCHBAR | 1);
pci_write_config32(PCI_DEV(0, 0x00, 0), MCHBAR + 4, (0LL+DEFAULT_MCHBAR) >> 32);
- pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR, DEFAULT_DMIBAR | 1);
- pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR + 4, (0LL+DEFAULT_DMIBAR) >> 32);
+ pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR, (uintptr_t)DEFAULT_DMIBAR | 1);
+ pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR + 4, (0LL+(uintptr_t)DEFAULT_DMIBAR) >> 32);
/* Set C0000-FFFFF to access RAM on both reads and writes */
pci_write_config8(PCI_DEV(0, 0x00, 0), PAM0, 0x30);
diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c
index 325edbd05..5d0e8e724 100644
--- a/src/northbridge/intel/haswell/gma.c
+++ b/src/northbridge/intel/haswell/gma.c
@@ -171,14 +171,14 @@ static struct resource *gtt_res = NULL;
u32 gtt_read(u32 reg)
{
u32 val;
- val = read32(gtt_res->base + reg);
+ val = read32(res2mmio(gtt_res, reg, 0));
return val;
}
void gtt_write(u32 reg, u32 data)
{
- write32(gtt_res->base + reg, data);
+ write32(res2mmio(gtt_res, reg, 0), data);
}
static inline void gtt_rmw(u32 reg, u32 andmask, u32 ormask)
diff --git a/src/northbridge/intel/haswell/haswell.h b/src/northbridge/intel/haswell/haswell.h
index d8221a986..b673f8154 100644
--- a/src/northbridge/intel/haswell/haswell.h
+++ b/src/northbridge/intel/haswell/haswell.h
@@ -32,7 +32,11 @@
/* Northbridge BARs */
#define DEFAULT_PCIEXBAR CONFIG_MMCONF_BASE_ADDRESS /* 4 KB per PCIe device */
#define DEFAULT_MCHBAR 0xfed10000 /* 16 KB */
+#ifndef __ACPI__
+#define DEFAULT_DMIBAR ((u8 *)0xfed18000) /* 4 KB */
+#else
#define DEFAULT_DMIBAR 0xfed18000 /* 4 KB */
+#endif
#define DEFAULT_EPBAR 0xfed19000 /* 4 KB */
#include <southbridge/intel/lynxpoint/pch.h>
diff --git a/src/northbridge/intel/haswell/minihd.c b/src/northbridge/intel/haswell/minihd.c
index 4a38b2855..f1b137e06 100644
--- a/src/northbridge/intel/haswell/minihd.c
+++ b/src/northbridge/intel/haswell/minihd.c
@@ -67,7 +67,8 @@ static const u32 minihd_verb_table[] = {
static void minihd_init(struct device *dev)
{
struct resource *res;
- u32 base, reg32;
+ u32 reg32;
+ u8 *base;
int codec_mask, i;
/* Find base address */
@@ -75,8 +76,8 @@ static void minihd_init(struct device *dev)
if (!res)
return;
- base = (u32)res->base;
- printk(BIOS_DEBUG, "Mini-HD: base = %08x\n", (u32)base);
+ base = res2mmio(res, 0, 0);
+ printk(BIOS_DEBUG, "Mini-HD: base = %p\n", base);
/* Set Bus Master */
reg32 = pci_read_config32(dev, PCI_COMMAND);
diff --git a/src/northbridge/intel/i3100/i3100.h b/src/northbridge/intel/i3100/i3100.h
index 2d036bd02..ac6f8c6b3 100644
--- a/src/northbridge/intel/i3100/i3100.h
+++ b/src/northbridge/intel/i3100/i3100.h
@@ -65,7 +65,7 @@
#define DRC_72BIT_ECC (1 << 20)
#define RCBA 0xF0
-#define DEFAULT_RCBA 0xFEA00000
+#define DEFAULT_RCBA ((u8 *)0xFEA00000)
int bios_reset_detected(void);
diff --git a/src/northbridge/intel/i3100/raminit.c b/src/northbridge/intel/i3100/raminit.c
index ebe137b90..34d1eefbb 100644
--- a/src/northbridge/intel/i3100/raminit.c
+++ b/src/northbridge/intel/i3100/raminit.c
@@ -28,7 +28,7 @@
#include "i3100.h"
/* DDR2 memory controller register space */
-#define MCBAR 0x90000000
+#define MCBAR ((u8 *)(0x90000000))
static void sdram_set_registers(const struct mem_controller *ctrl)
{
@@ -61,7 +61,7 @@ static void sdram_set_registers(const struct mem_controller *ctrl)
PCI_ADDR(0, 0x00, 0, DEVPRES1), 0xffbffff, (1<<22)|(6<<2) | DEVPRES1_CONFIG,
/* 0x14 */
- PCI_ADDR(0, 0x00, 0, IURBASE), 0x00000fff, MCBAR |0,
+ PCI_ADDR(0, 0x00, 0, IURBASE), 0x00000fff, (uintptr_t)(MCBAR + 0),
};
int i;
int max;
@@ -936,6 +936,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
int i;
int cs;
int cnt;
+ u8 *cntptr;
int cas_latency;
long mask;
u32 drc;
@@ -1139,8 +1140,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
/* DQS */
pci_write_config32(ctrl->f0, 0x94, 0x3904aa00);
- for(i = 0, cnt = (MCBAR+0x200); i < 24; i++, cnt+=4) {
- write32(cnt, dqs_data[i]);
+ for(i = 0, cntptr = (MCBAR+0x200); i < 24; i++, cnt+=4) {
+ write32(cntptr, dqs_data[i]);
}
pci_write_config32(ctrl->f0, 0x94, 0x3900aa00);
diff --git a/src/northbridge/intel/i3100/raminit_ep80579.c b/src/northbridge/intel/i3100/raminit_ep80579.c
index b2858e4a8..77d4463e0 100644
--- a/src/northbridge/intel/i3100/raminit_ep80579.c
+++ b/src/northbridge/intel/i3100/raminit_ep80579.c
@@ -25,7 +25,7 @@
#include "raminit_ep80579.h"
#include "ep80579.h"
-#define BAR 0x90000000
+#define BAR ((u8 *)0x90000000)
static void sdram_set_registers(const struct mem_controller *ctrl)
{
@@ -35,7 +35,7 @@ static void sdram_set_registers(const struct mem_controller *ctrl)
PCI_ADDR(0, 0x00, 0, PAM-1), 0xcccccc7f, 0x33333000,
PCI_ADDR(0, 0x00, 0, PAM+3), 0xcccccccc, 0x33333333,
PCI_ADDR(0, 0x00, 0, DEVPRES1), 0xffffffff, 0x0040003a,
- PCI_ADDR(0, 0x00, 0, SMRBASE), 0x00000fff, BAR | 0,
+ PCI_ADDR(0, 0x00, 0, SMRBASE), 0x00000fff, (uintptr_t)BAR | 0,
};
int i;
diff --git a/src/northbridge/intel/i440bx/raminit.c b/src/northbridge/intel/i440bx/raminit.c
index f191abe13..bed2a51a6 100644
--- a/src/northbridge/intel/i440bx/raminit.c
+++ b/src/northbridge/intel/i440bx/raminit.c
@@ -387,7 +387,8 @@ static void do_ram_command(u32 command)
int i, caslatency;
u8 dimm_start, dimm_end;
u16 reg16;
- u32 addr, addr_offset;
+ void *addr;
+ u32 addr_offset;
/* Configure the RAM command. */
reg16 = pci_read_config16(NB, SDRAMC);
@@ -424,7 +425,7 @@ static void do_ram_command(u32 command)
dimm_end = pci_read_config8(NB, DRB + i);
- addr = (dimm_start * 8 * 1024 * 1024) + addr_offset;
+ addr = (void *)((dimm_start * 8 * 1024 * 1024) + addr_offset);
if (dimm_end > dimm_start) {
#if 0
PRINT_DEBUG(" Sending RAM command 0x%04x to 0x%08x\n",
diff --git a/src/northbridge/intel/i5000/raminit.h b/src/northbridge/intel/i5000/raminit.h
index aa140928d..021e6fa32 100644
--- a/src/northbridge/intel/i5000/raminit.h
+++ b/src/northbridge/intel/i5000/raminit.h
@@ -151,7 +151,7 @@
#define I5000_DMIR3 0x9c
#define I5000_DMIR4 0xa0
-#define DEFAULT_AMBASE 0xfe000000
+#define DEFAULT_AMBASE ((u8 *)0xfe000000)
/* AMB function 1 registers */
#define AMB_FBDSBCFGNXT 0x54
diff --git a/src/northbridge/intel/i82810/raminit.c b/src/northbridge/intel/i82810/raminit.c
index b45180351..dddfaa40e 100644
--- a/src/northbridge/intel/i82810/raminit.c
+++ b/src/northbridge/intel/i82810/raminit.c
@@ -138,7 +138,7 @@ SDRAM configuration functions.
*/
static void do_ram_command(u8 command)
{
- u32 addr, addr_offset;
+ u32 *addr, addr_offset;
u16 dimm_size, dimm_start, dimm_bank;
u8 reg8, drp;
int i, caslatency;
@@ -191,15 +191,15 @@ static void do_ram_command(u8 command)
dimm_size = translate_i82810_to_mb[drp];
if (dimm_size) {
- addr = (dimm_start * 1024 * 1024) + addr_offset;
- PRINT_DEBUG(" Sending RAM command 0x%02x to 0x%08x\n", reg8, addr);
+ addr = (u32 *)((dimm_start * 1024 * 1024) + addr_offset);
+ PRINT_DEBUG(" Sending RAM command 0x%02x to 0x%p\n", reg8, addr);
read32(addr);
}
dimm_bank = translate_i82810_to_bank[drp];
if (dimm_bank) {
- addr = ((dimm_start + dimm_bank) * 1024 * 1024) + addr_offset;
- PRINT_DEBUG(" Sending RAM command 0x%02x to 0x%08x\n", reg8, addr);
+ addr = (u32 *)(((dimm_start + dimm_bank) * 1024 * 1024) + addr_offset);
+ PRINT_DEBUG(" Sending RAM command 0x%02x to 0x%p\n", reg8, addr);
read32(addr);
}
diff --git a/src/northbridge/intel/i82830/raminit.c b/src/northbridge/intel/i82830/raminit.c
index a42374c10..bff59bf3a 100644
--- a/src/northbridge/intel/i82830/raminit.c
+++ b/src/northbridge/intel/i82830/raminit.c
@@ -77,15 +77,15 @@ static void ram_read32(u8 dimm_start, u32 offset)
{
u32 reg32, base_addr = 32 * 1024 * 1024 * dimm_start;
if (offset == 0x55aa55aa) {
- reg32 = read32(base_addr);
+ reg32 = read32((u32 *)base_addr);
PRINTK_DEBUG(" Reading RAM at 0x%08x => 0x%08x\n", base_addr, reg32);
PRINTK_DEBUG(" Writing RAM at 0x%08x <= 0x%08x\n", base_addr, offset);
- write32(base_addr, offset);
- reg32 = read32(base_addr);
+ write32((u32 *)base_addr, offset);
+ reg32 = read32((u32 *)base_addr);
PRINTK_DEBUG(" Reading RAM at 0x%08x => 0x%08x\n", base_addr, reg32);
} else {
PRINTK_DEBUG(" to 0x%08x\n", base_addr + offset);
- read32(base_addr + offset);
+ read32((u32 *)(base_addr + offset));
}
}
diff --git a/src/northbridge/intel/i82830/smihandler.c b/src/northbridge/intel/i82830/smihandler.c
index e4d93cfe6..b50c88429 100644
--- a/src/northbridge/intel/i82830/smihandler.c
+++ b/src/northbridge/intel/i82830/smihandler.c
@@ -297,7 +297,7 @@ static void mbi_call(u8 subf, banner_id_t *banner_id)
static void smi_interface_call(void)
{
- u32 mmio = pci_read_config32(PCI_DEV(0, 0x02, 0), 0x14);
+ u8 *mmio = (u8 *)pci_read_config32(PCI_DEV(0, 0x02, 0), 0x14);
// mmio &= 0xfff80000;
// printk(BIOS_DEBUG, "mmio=%x\n", mmio);
u16 swsmi = pci_read_config16(PCI_DEV(0, 0x02, 0), 0xe0);
diff --git a/src/northbridge/intel/i855/raminit.c b/src/northbridge/intel/i855/raminit.c
index 39e12d2d0..f0cc5a90b 100644
--- a/src/northbridge/intel/i855/raminit.c
+++ b/src/northbridge/intel/i855/raminit.c
@@ -393,7 +393,7 @@ static void do_ram_command(uint8_t command, uint16_t jedec_mode_bits)
uint32_t dimm_start_address = dimm_start_32M_multiple << 25;
PRINTK_DEBUG(" Sending RAM command to 0x%08x\n", dimm_start_address + i855_mode_bits);
- read32(dimm_start_address + i855_mode_bits);
+ read32((void *)(dimm_start_address + i855_mode_bits));
// Set the start of the next DIMM
dimm_start_32M_multiple = dimm_end_32M_multiple;
diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c
index 0b2acd70b..776c05133 100644
--- a/src/northbridge/intel/i945/early_init.c
+++ b/src/northbridge/intel/i945/early_init.c
@@ -156,7 +156,7 @@ static void i945_setup_bars(void)
/* Setting up Southbridge. In the northbridge code. */
printk(BIOS_DEBUG, "Setting up static southbridge registers...");
- pci_write_config32(PCI_DEV(0, 0x1f, 0), RCBA, DEFAULT_RCBA | 1);
+ pci_write_config32(PCI_DEV(0, 0x1f, 0), RCBA, (uintptr_t)DEFAULT_RCBA | 1);
pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, DEFAULT_PMBASE | 1);
pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44 /* ACPI_CNTL */ , 0x80); /* Enable ACPI BAR */
@@ -177,8 +177,8 @@ static void i945_setup_bars(void)
printk(BIOS_DEBUG, "Setting up static northbridge registers...");
/* Set up all hardcoded northbridge BARs */
pci_write_config32(PCI_DEV(0, 0x00, 0), EPBAR, DEFAULT_EPBAR | 1);
- pci_write_config32(PCI_DEV(0, 0x00, 0), MCHBAR, DEFAULT_MCHBAR | 1);
- pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR, DEFAULT_DMIBAR | 1);
+ pci_write_config32(PCI_DEV(0, 0x00, 0), MCHBAR, (uintptr_t)DEFAULT_MCHBAR | 1);
+ pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR, (uintptr_t)DEFAULT_DMIBAR | 1);
pci_write_config32(PCI_DEV(0, 0x00, 0), X60BAR, DEFAULT_X60BAR | 1);
/* Hardware default is 8MB UMA. If someone wants to make this a
@@ -342,7 +342,7 @@ static void ich7_setup_dmi_rcrb(void)
RCBA32(ULD) |= (1 << 24) | (1 << 16);
- RCBA32(ULBA) = DEFAULT_DMIBAR;
+ RCBA32(ULBA) = (uintptr_t)DEFAULT_DMIBAR;
RCBA32(RP1D) |= (2 << 16);
RCBA32(RP2D) |= (2 << 16);
@@ -818,7 +818,7 @@ static void i945_setup_root_complex_topology(void)
EPBAR32(EPLE1D) |= (1 << 16) | (1 << 0);
- EPBAR32(EPLE1A) = DEFAULT_DMIBAR;
+ EPBAR32(EPLE1A) = (uintptr_t)DEFAULT_DMIBAR;
EPBAR32(EPLE2D) |= (1 << 16) | (1 << 0);
@@ -833,7 +833,7 @@ static void i945_setup_root_complex_topology(void)
reg32 |= (1 << 0);
DMIBAR32(DMILE1D) = reg32;
- DMIBAR32(DMILE1A) = DEFAULT_RCBA;
+ DMIBAR32(DMILE1A) = (uintptr_t)DEFAULT_RCBA;
DMIBAR32(DMILE2D) |= (1 << 16) | (1 << 0);
diff --git a/src/northbridge/intel/i945/i945.h b/src/northbridge/intel/i945/i945.h
index fe59ebe9b..7d02b3773 100644
--- a/src/northbridge/intel/i945/i945.h
+++ b/src/northbridge/intel/i945/i945.h
@@ -23,8 +23,13 @@
/* Northbridge BARs */
#define DEFAULT_PCIEXBAR CONFIG_MMCONF_BASE_ADDRESS /* 4 KB per PCIe device */
#define DEFAULT_X60BAR 0xfed13000
+#ifndef __ACPI__
+#define DEFAULT_MCHBAR ((u8 *)0xfed14000) /* 16 KB */
+#define DEFAULT_DMIBAR ((u8 *)0xfed18000) /* 4 KB */
+#else
#define DEFAULT_MCHBAR 0xfed14000 /* 16 KB */
#define DEFAULT_DMIBAR 0xfed18000 /* 4 KB */
+#endif
#define DEFAULT_EPBAR 0xfed19000 /* 4 KB */
#include "../../../southbridge/intel/i82801gx/i82801gx.h"
diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c
index 0a6011286..c3f9bae06 100644
--- a/src/northbridge/intel/i945/raminit.c
+++ b/src/northbridge/intel/i945/raminit.c
@@ -90,7 +90,7 @@ static void ram_read32(u32 offset)
{
PRINTK_DEBUG(" ram read: %08x\n", offset);
- read32(offset);
+ read32((void *)offset);
}
#if CONFIG_DEBUG_RAM_SETUP
diff --git a/src/northbridge/intel/i945/rcven.c b/src/northbridge/intel/i945/rcven.c
index 88d6a00cd..6d429e44a 100644
--- a/src/northbridge/intel/i945/rcven.c
+++ b/src/northbridge/intel/i945/rcven.c
@@ -42,8 +42,8 @@ static u32 sample_strobes(int channel_offset, struct sys_info *sysinfo)
}
for (i = 0; i < 28; i++) {
- read32(addr);
- read32(addr + 0x80);
+ read32((void *)addr);
+ read32((void *)(addr + 0x80));
}
reg32 = MCHBAR32(RCVENMT);
diff --git a/src/northbridge/intel/nehalem/acpi.c b/src/northbridge/intel/nehalem/acpi.c
index 460942f12..4a208ce5e 100644
--- a/src/northbridge/intel/nehalem/acpi.c
+++ b/src/northbridge/intel/nehalem/acpi.c
@@ -120,7 +120,7 @@ static int init_opregion_vbt(igd_opregion_t * opregion)
optionrom_header_t *oprom = (optionrom_header_t *) vbios;
optionrom_vbt_t *vbt = (optionrom_vbt_t *) (vbios + oprom->vbt_offset);
- if (read32((unsigned long)vbt->hdr_signature) != VBT_SIGNATURE) {
+ if (read32(vbt->hdr_signature) != VBT_SIGNATURE) {
printk(BIOS_DEBUG, "VBT not found!\n");
return 1;
}
diff --git a/src/northbridge/intel/nehalem/early_init.c b/src/northbridge/intel/nehalem/early_init.c
index ee8c17a18..56c0d6872 100644
--- a/src/northbridge/intel/nehalem/early_init.c
+++ b/src/northbridge/intel/nehalem/early_init.c
@@ -36,7 +36,7 @@ static void nehalem_setup_bars(void)
{
/* Setting up Southbridge. In the northbridge code. */
printk(BIOS_DEBUG, "Setting up static southbridge registers...");
- pci_write_config32(PCI_DEV(0, 0x1f, 0), RCBA, DEFAULT_RCBA | 1);
+ pci_write_config32(PCI_DEV(0, 0x1f, 0), RCBA, (uintptr_t)DEFAULT_RCBA | 1);
pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, DEFAULT_PMBASE | 1);
/* Enable ACPI BAR */
@@ -59,13 +59,13 @@ static void nehalem_setup_bars(void)
pci_write_config32(PCI_DEV(0, 0x00, 0), EPBAR, DEFAULT_EPBAR | 1);
pci_write_config32(PCI_DEV(0, 0x00, 0), EPBAR + 4,
(0LL + DEFAULT_EPBAR) >> 32);
- pci_write_config32(PCI_DEV(0, 0x00, 0), MCHBAR, DEFAULT_MCHBAR | 1);
+ pci_write_config32(PCI_DEV(0, 0x00, 0), MCHBAR, (uintptr_t)DEFAULT_MCHBAR | 1);
pci_write_config32(PCI_DEV(0, 0x00, 0), MCHBAR + 4,
- (0LL + DEFAULT_MCHBAR) >> 32);
+ (0LL + (uintptr_t)DEFAULT_MCHBAR) >> 32);
- pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR, DEFAULT_DMIBAR | 1);
+ pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR, (uintptr_t)DEFAULT_DMIBAR | 1);
pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR + 4,
- (0LL + DEFAULT_DMIBAR) >> 32);
+ (0LL + (uintptr_t)DEFAULT_DMIBAR) >> 32);
/* Set C0000-FFFFF to access RAM on both reads and writes */
pci_write_config8(PCI_DEV(0xff, 0x00, 1), QPD0F1_PAM(0), 0x30);
@@ -163,7 +163,7 @@ void nehalem_early_initialization(int chipset_type)
early_cpu_init();
- pci_write_config32(PCI_DEV(0, 0x16, 0), 0x10, DEFAULT_HECIBAR);
+ pci_write_config32(PCI_DEV(0, 0x16, 0), 0x10, (uintptr_t)DEFAULT_HECIBAR);
pci_write_config32(PCI_DEV(0, 0x16, 0), PCI_COMMAND,
PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
diff --git a/src/northbridge/intel/nehalem/gma.c b/src/northbridge/intel/nehalem/gma.c
index c3e2a492c..9fc4bd45b 100644
--- a/src/northbridge/intel/nehalem/gma.c
+++ b/src/northbridge/intel/nehalem/gma.c
@@ -274,12 +274,12 @@ static struct resource *gtt_res = NULL;
u32 gtt_read(u32 reg)
{
- return read32(gtt_res->base + reg);
+ return read32(res2mmio(gtt_res, reg, 0));
}
void gtt_write(u32 reg, u32 data)
{
- write32(gtt_res->base + reg, data);
+ write32(res2mmio(gtt_res, reg, 0), data);
}
static inline void gtt_write_powermeter(const struct gt_powermeter *pm)
@@ -561,7 +561,7 @@ static void gma_pm_init_post_vbios(struct device *dev)
#if IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT)
-static void train_link(u32 mmio)
+static void train_link(u8 *mmio)
{
/* Clear interrupts. */
write32(mmio + DEIIR, 0xffffffff);
@@ -584,7 +584,7 @@ static void train_link(u32 mmio)
read32(mmio + 0x000f0014); // = 0x00000600
}
-static void power_port(u32 mmio)
+static void power_port(u8 *mmio)
{
read32(mmio + 0x000e1100); // = 0x00000000
write32(mmio + 0x000e1100, 0x00000000);
@@ -639,7 +639,7 @@ static void power_port(u32 mmio)
}
static void intel_gma_init(const struct northbridge_intel_nehalem_config *info,
- u32 mmio, u32 physbase, u16 piobase, u32 lfb)
+ u8 *mmio, u32 physbase, u16 piobase, u32 lfb)
{
int i;
u8 edid_data[128];
@@ -1020,8 +1020,8 @@ static void gma_func0_init(struct device *dev)
&& lfb_res && lfb_res->base) {
printk(BIOS_SPEW, "Initializing VGA without OPROM. MMIO 0x%llx\n",
gtt_res->base);
- intel_gma_init(conf, gtt_res->base, physbase, pio_res->base,
- lfb_res->base);
+ intel_gma_init(conf, res2mmio(gtt_res, 0, 0), physbase,
+ pio_res->base, lfb_res->base);
}
/* Linux relies on VBT for panel info. */
diff --git a/src/northbridge/intel/nehalem/nehalem.h b/src/northbridge/intel/nehalem/nehalem.h
index 73137b21e..b90e5a910 100644
--- a/src/northbridge/intel/nehalem/nehalem.h
+++ b/src/northbridge/intel/nehalem/nehalem.h
@@ -186,7 +186,7 @@ enum {
(could be reduced to 10 bytes) */
-#define DEFAULT_HECIBAR 0xfed17000
+#define DEFAULT_HECIBAR ((u8 *)0xfed17000)
/* 4 KB per PCIe device */
#define DEFAULT_PCIEXBAR CONFIG_MMCONF_BASE_ADDRESS
@@ -454,10 +454,15 @@ void init_iommu(void);
/* Northbridge BARs */
#define DEFAULT_PCIEXBAR CONFIG_MMCONF_BASE_ADDRESS /* 4 KB per PCIe device */
+#ifndef __ACPI__
+#define DEFAULT_MCHBAR ((u8 *)0xfed10000) /* 16 KB */
+#define DEFAULT_DMIBAR ((u8 *)0xfed18000) /* 4 KB */
+#else
#define DEFAULT_MCHBAR 0xfed10000 /* 16 KB */
#define DEFAULT_DMIBAR 0xfed18000 /* 4 KB */
+#endif
#define DEFAULT_EPBAR 0xfed19000 /* 4 KB */
-#define DEFAULT_RCBABASE 0xfed1c000
+#define DEFAULT_RCBABASE ((u8 *)0xfed1c000)
#define QUICKPATH_BUS 0xff
diff --git a/src/northbridge/intel/nehalem/raminit.c b/src/northbridge/intel/nehalem/raminit.c
index 85c82c9e9..3917288e5 100644
--- a/src/northbridge/intel/nehalem/raminit.c
+++ b/src/northbridge/intel/nehalem/raminit.c
@@ -200,6 +200,16 @@ static u16 read_1d0(u16 addr, int split)
return val;
}
+static void write32p(uintptr_t addr, uint32_t val)
+{
+ write32((void *)addr, val);
+}
+
+static uint32_t read32p(uintptr_t addr)
+{
+ return read32((void *)addr);
+}
+
static void sfence(void)
{
#if REAL
@@ -314,36 +324,36 @@ static int rw_test(int rank)
int ok = 0xff;
int i;
for (i = 0; i < 64; i++)
- write32((rank << 28) | (i << 2), 0);
+ write32p((rank << 28) | (i << 2), 0);
sfence();
for (i = 0; i < 64; i++)
- gav(read32((rank << 28) | (i << 2)));
+ gav(read32p((rank << 28) | (i << 2)));
sfence();
for (i = 0; i < 32; i++) {
u32 pat = (((mask >> i) & 1) ? 0xffffffff : 0);
- write32((rank << 28) | (i << 3), pat);
- write32((rank << 28) | (i << 3) | 4, pat);
+ write32p((rank << 28) | (i << 3), pat);
+ write32p((rank << 28) | (i << 3) | 4, pat);
}
sfence();
for (i = 0; i < 32; i++) {
u8 pat = (((mask >> i) & 1) ? 0xff : 0);
int j;
u32 val;
- gav(val = read32((rank << 28) | (i << 3)));
+ gav(val = read32p((rank << 28) | (i << 3)));
for (j = 0; j < 4; j++)
if (((val >> (j * 8)) & 0xff) != pat)
ok &= ~(1 << j);
- gav(val = read32((rank << 28) | (i << 3) | 4));
+ gav(val = read32p((rank << 28) | (i << 3) | 4));
for (j = 0; j < 4; j++)
if (((val >> (j * 8)) & 0xff) != pat)
ok &= ~(16 << j);
}
sfence();
for (i = 0; i < 64; i++)
- write32((rank << 28) | (i << 2), 0);
+ write32p((rank << 28) | (i << 2), 0);
sfence();
for (i = 0; i < 64; i++)
- gav(read32((rank << 28) | (i << 2)));
+ gav(read32p((rank << 28) | (i << 2)));
return ok;
}
@@ -1072,12 +1082,12 @@ static void jedec_read(struct raminfo *info,
(value & ~0x1f8) | ((value >> 1) & 0xa8) | ((value & 0xa8)
<< 1);
- read32((value << 3) | (total_rank << 28));
+ read32p((value << 3) | (total_rank << 28));
write_mchbar8(0x271, (read_mchbar8(0x271) & 0xC3) | 2);
write_mchbar8(0x671, (read_mchbar8(0x671) & 0xC3) | 2);
- read32(total_rank << 28);
+ read32p(total_rank << 28);
}
enum {
@@ -1562,7 +1572,7 @@ static void collect_system_info(struct raminfo *info)
unsigned channel;
/* Wait for some bit, maybe TXT clear. */
- while (!(read8(0xfed40000) & (1 << 7))) ;
+ while (!(read8((u8 *)0xfed40000) & (1 << 7))) ;
if (!info->heci_bar)
gav(info->heci_bar =
@@ -1746,9 +1756,9 @@ static const struct ram_training *get_cached_training(void)
/* FIXME: add timeout. */
static void wait_heci_ready(void)
{
- while (!(read32(DEFAULT_HECIBAR | 0xc) & 8)) ; // = 0x8000000c
- write32((DEFAULT_HECIBAR | 0x4),
- (read32(DEFAULT_HECIBAR | 0x4) & ~0x10) | 0xc);
+ while (!(read32(DEFAULT_HECIBAR + 0xc) & 8)) ; // = 0x8000000c
+ write32((DEFAULT_HECIBAR + 0x4),
+ (read32(DEFAULT_HECIBAR + 0x4) & ~0x10) | 0xc);
}
/* FIXME: add timeout. */
@@ -1759,10 +1769,10 @@ static void wait_heci_cb_avail(int len)
u32 raw;
} csr;
- while (!(read32(DEFAULT_HECIBAR | 0xc) & 8)) ;
+ while (!(read32(DEFAULT_HECIBAR + 0xc) & 8)) ;
do
- csr.raw = read32(DEFAULT_HECIBAR | 0x4);
+ csr.raw = read32(DEFAULT_HECIBAR + 0x4);
while (len >
csr.csr.buffer_depth - (csr.csr.buffer_write_ptr -
csr.csr.buffer_read_ptr));
@@ -1776,12 +1786,12 @@ static void send_heci_packet(struct mei_header *head, u32 * payload)
wait_heci_cb_avail(len + 1);
/* FIXME: handle leftovers correctly. */
- write32(DEFAULT_HECIBAR | 0, *(u32 *) head);
+ write32(DEFAULT_HECIBAR + 0, *(u32 *) head);
for (i = 0; i < len - 1; i++)
- write32(DEFAULT_HECIBAR | 0, payload[i]);
+ write32(DEFAULT_HECIBAR + 0, payload[i]);
- write32(DEFAULT_HECIBAR | 0, payload[i] & ((1 << (8 * len)) - 1));
- write32(DEFAULT_HECIBAR | 0x4, read32(DEFAULT_HECIBAR | 0x4) | 0x4);
+ write32(DEFAULT_HECIBAR + 0, payload[i] & ((1 << (8 * len)) - 1));
+ write32(DEFAULT_HECIBAR + 0x4, read32(DEFAULT_HECIBAR + 0x4) | 0x4);
}
static void
@@ -1791,7 +1801,7 @@ send_heci_message(u8 * msg, int len, u8 hostaddress, u8 clientaddress)
int maxlen;
wait_heci_ready();
- maxlen = (read32(DEFAULT_HECIBAR | 0x4) >> 24) * 4 - 4;
+ maxlen = (read32(DEFAULT_HECIBAR + 0x4) >> 24) * 4 - 4;
while (len) {
int cur = len;
@@ -1821,19 +1831,19 @@ recv_heci_packet(struct raminfo *info, struct mei_header *head, u32 * packet,
} csr;
int i = 0;
- write32(DEFAULT_HECIBAR | 0x4, read32(DEFAULT_HECIBAR | 0x4) | 2);
+ write32(DEFAULT_HECIBAR + 0x4, read32(DEFAULT_HECIBAR + 0x4) | 2);
do {
- csr.raw = read32(DEFAULT_HECIBAR | 0xc);
+ csr.raw = read32(DEFAULT_HECIBAR + 0xc);
#if !REAL
if (i++ > 346)
return -1;
#endif
}
while (csr.csr.buffer_write_ptr == csr.csr.buffer_read_ptr);
- *(u32 *) head = read32(DEFAULT_HECIBAR | 0x8);
+ *(u32 *) head = read32(DEFAULT_HECIBAR + 0x8);
if (!head->length) {
- write32(DEFAULT_HECIBAR | 0x4,
- read32(DEFAULT_HECIBAR | 0x4) | 2);
+ write32(DEFAULT_HECIBAR + 0x4,
+ read32(DEFAULT_HECIBAR + 0x4) | 2);
*packet_size = 0;
return 0;
}
@@ -1844,16 +1854,16 @@ recv_heci_packet(struct raminfo *info, struct mei_header *head, u32 * packet,
}
do
- csr.raw = read32(DEFAULT_HECIBAR | 0xc);
+ csr.raw = read32(DEFAULT_HECIBAR + 0xc);
while ((head->length + 3) >> 2 >
csr.csr.buffer_write_ptr - csr.csr.buffer_read_ptr);
for (i = 0; i < (head->length + 3) >> 2; i++)
- packet[i++] = read32(DEFAULT_HECIBAR | 0x8);
+ packet[i++] = read32(DEFAULT_HECIBAR + 0x8);
*packet_size = head->length;
if (!csr.csr.ready)
*packet_size = 0;
- write32(DEFAULT_HECIBAR | 0x4, read32(DEFAULT_HECIBAR | 0x4) | 4);
+ write32(DEFAULT_HECIBAR + 0x4, read32(DEFAULT_HECIBAR + 0x4) | 4);
return 0;
}
@@ -1941,27 +1951,27 @@ static void setup_heci_uma(struct raminfo *info)
pcie_read_config32(NORTHBRIDGE, DMIBAR);
if (info->memory_reserved_for_heci_mb) {
- write32(DEFAULT_DMIBAR | 0x14,
- read32(DEFAULT_DMIBAR | 0x14) & ~0x80);
- write32(DEFAULT_RCBA | 0x14,
- read32(DEFAULT_RCBA | 0x14) & ~0x80);
- write32(DEFAULT_DMIBAR | 0x20,
- read32(DEFAULT_DMIBAR | 0x20) & ~0x80);
- write32(DEFAULT_RCBA | 0x20,
- read32(DEFAULT_RCBA | 0x20) & ~0x80);
- write32(DEFAULT_DMIBAR | 0x2c,
- read32(DEFAULT_DMIBAR | 0x2c) & ~0x80);
- write32(DEFAULT_RCBA | 0x30,
- read32(DEFAULT_RCBA | 0x30) & ~0x80);
- write32(DEFAULT_DMIBAR | 0x38,
- read32(DEFAULT_DMIBAR | 0x38) & ~0x80);
- write32(DEFAULT_RCBA | 0x40,
- read32(DEFAULT_RCBA | 0x40) & ~0x80);
-
- write32(DEFAULT_RCBA | 0x40, 0x87000080); // OK
- write32(DEFAULT_DMIBAR | 0x38, 0x87000080); // OK
- while (read16(DEFAULT_RCBA | 0x46) & 2
- && read16(DEFAULT_DMIBAR | 0x3e) & 2) ;
+ write32(DEFAULT_DMIBAR + 0x14,
+ read32(DEFAULT_DMIBAR + 0x14) & ~0x80);
+ write32(DEFAULT_RCBA + 0x14,
+ read32(DEFAULT_RCBA + 0x14) & ~0x80);
+ write32(DEFAULT_DMIBAR + 0x20,
+ read32(DEFAULT_DMIBAR + 0x20) & ~0x80);
+ write32(DEFAULT_RCBA + 0x20,
+ read32(DEFAULT_RCBA + 0x20) & ~0x80);
+ write32(DEFAULT_DMIBAR + 0x2c,
+ read32(DEFAULT_DMIBAR + 0x2c) & ~0x80);
+ write32(DEFAULT_RCBA + 0x30,
+ read32(DEFAULT_RCBA + 0x30) & ~0x80);
+ write32(DEFAULT_DMIBAR + 0x38,
+ read32(DEFAULT_DMIBAR + 0x38) & ~0x80);
+ write32(DEFAULT_RCBA + 0x40,
+ read32(DEFAULT_RCBA + 0x40) & ~0x80);
+
+ write32(DEFAULT_RCBA + 0x40, 0x87000080); // OK
+ write32(DEFAULT_DMIBAR + 0x38, 0x87000080); // OK
+ while (read16(DEFAULT_RCBA + 0x46) & 2
+ && read16(DEFAULT_DMIBAR + 0x3e) & 2) ;
}
write_mchbar32(0x24, 0x10000 + info->memory_reserved_for_heci_mb);
@@ -2092,9 +2102,9 @@ static void write_testing(struct raminfo *info, int totalrank, int flip)
int nwrites = 0;
/* in 8-byte units. */
u32 offset;
- u32 base;
+ u8 *base;
- base = totalrank << 28;
+ base = (u8 *)(totalrank << 28);
for (offset = 0; offset < 9 * 480; offset += 2) {
write32(base + offset * 8, get_etalon2(flip, offset));
write32(base + offset * 8 + 4, get_etalon2(flip, offset));
@@ -2212,8 +2222,8 @@ write_testing_type2(struct raminfo *info, u8 totalrank, u8 region, u8 block,
{
int i;
for (i = 0; i < 2048; i++)
- write32((totalrank << 28) | (region << 25) | (block << 16) |
- (i << 2), get_etalon(flip, (block << 16) | (i << 2)));
+ write32p((totalrank << 28) | (region << 25) | (block << 16) |
+ (i << 2), get_etalon(flip, (block << 16) | (i << 2)));
}
static u8
@@ -2238,7 +2248,7 @@ check_testing_type2(struct raminfo *info, u8 totalrank, u8 region, u8 block,
| (comp3 << 12) | (comp2 << 6) | (comp1 <<
2);
failxor[comp1 & 1] |=
- read32(addr) ^ get_etalon(flip, addr);
+ read32p(addr) ^ get_etalon(flip, addr);
}
for (i = 0; i < 8; i++)
if ((0xff << (8 * (i % 4))) & failxor[i / 4])
@@ -3774,13 +3784,13 @@ static void restore_274265(struct raminfo *info)
#if REAL
static void dmi_setup(void)
{
- gav(read8(DEFAULT_DMIBAR | 0x254));
- write8(DEFAULT_DMIBAR | 0x254, 0x1);
- write16(DEFAULT_DMIBAR | 0x1b8, 0x18f2);
+ gav(read8(DEFAULT_DMIBAR + 0x254));
+ write8(DEFAULT_DMIBAR + 0x254, 0x1);
+ write16(DEFAULT_DMIBAR + 0x1b8, 0x18f2);
read_mchbar16(0x48);
write_mchbar16(0x48, 0x2);
- write32(DEFAULT_DMIBAR | 0xd68, read32(DEFAULT_DMIBAR | 0xd68) | 0x08000000);
+ write32(DEFAULT_DMIBAR + 0xd68, read32(DEFAULT_DMIBAR + 0xd68) | 0x08000000);
outl((gav(inl(DEFAULT_GPIOBASE | 0x38)) & ~0x140000) | 0x400000,
DEFAULT_GPIOBASE | 0x38);
@@ -3842,18 +3852,18 @@ void chipset_init(const int s3resume)
write_mchbar32(0x2c44, 0x1053687);
pcie_read_config8(GMA, 0x62); // = 0x2
pcie_write_config8(GMA, 0x62, 0x2);
- read8(DEFAULT_RCBA | 0x2318);
- write8(DEFAULT_RCBA | 0x2318, 0x47);
- read8(DEFAULT_RCBA | 0x2320);
- write8(DEFAULT_RCBA | 0x2320, 0xfc);
+ read8(DEFAULT_RCBA + 0x2318);
+ write8(DEFAULT_RCBA + 0x2318, 0x47);
+ read8(DEFAULT_RCBA + 0x2320);
+ write8(DEFAULT_RCBA + 0x2320, 0xfc);
}
read_mchbar32(0x30);
write_mchbar32(0x30, 0x40);
pcie_write_config16(NORTHBRIDGE, D0F0_GGC, ggc);
- gav(read32(DEFAULT_RCBA | 0x3428));
- write32(DEFAULT_RCBA | 0x3428, 0x1d);
+ gav(read32(DEFAULT_RCBA + 0x3428));
+ write32(DEFAULT_RCBA + 0x3428, 0x1d);
}
void raminit(const int s3resume, const u8 *spd_addrmap)
@@ -4813,17 +4823,17 @@ void raminit(const int s3resume, const u8 *spd_addrmap)
write_mchbar32(0xd40, IOMMU_BASE1 | 1);
write_mchbar32(0xdc0, IOMMU_BASE4 | 1);
- write32(IOMMU_BASE1 | 0xffc, 0x80000000);
- write32(IOMMU_BASE2 | 0xffc, 0xc0000000);
- write32(IOMMU_BASE4 | 0xffc, 0x80000000);
+ write32p(IOMMU_BASE1 | 0xffc, 0x80000000);
+ write32p(IOMMU_BASE2 | 0xffc, 0xc0000000);
+ write32p(IOMMU_BASE4 | 0xffc, 0x80000000);
#else
{
u32 eax;
- eax = read32(0xffc + (read_mchbar32(0xd00) & ~1)) | 0x08000000; // = 0xe911714b// OK
- write32(0xffc + (read_mchbar32(0xd00) & ~1), eax); // OK
- eax = read32(0xffc + (read_mchbar32(0xdc0) & ~1)) | 0x40000000; // = 0xe911714b// OK
- write32(0xffc + (read_mchbar32(0xdc0) & ~1), eax); // OK
+ eax = read32p(0xffc + (read_mchbar32(0xd00) & ~1)) | 0x08000000; // = 0xe911714b// OK
+ write32p(0xffc + (read_mchbar32(0xd00) & ~1), eax); // OK
+ eax = read32p(0xffc + (read_mchbar32(0xdc0) & ~1)) | 0x40000000; // = 0xe911714b// OK
+ write32p(0xffc + (read_mchbar32(0xdc0) & ~1), eax); // OK
}
#endif
@@ -4870,9 +4880,9 @@ void raminit(const int s3resume, const u8 *spd_addrmap)
}
u32 reg1c;
pcie_read_config32(NORTHBRIDGE, 0x40); // = DEFAULT_EPBAR | 0x001 // OK
- reg1c = read32(DEFAULT_EPBAR | 0x01c); // = 0x8001 // OK
+ reg1c = read32p(DEFAULT_EPBAR | 0x01c); // = 0x8001 // OK
pcie_read_config32(NORTHBRIDGE, 0x40); // = DEFAULT_EPBAR | 0x001 // OK
- write32(DEFAULT_EPBAR | 0x01c, reg1c); // OK
+ write32p(DEFAULT_EPBAR | 0x01c, reg1c); // OK
read_mchbar8(0xe08); // = 0x0
pcie_read_config32(NORTHBRIDGE, 0xe4); // = 0x316126
write_mchbar8(0x1210, read_mchbar8(0x1210) | 2); // OK
diff --git a/src/northbridge/intel/sandybridge/acpi.c b/src/northbridge/intel/sandybridge/acpi.c
index 7a4869654..71eb9df3d 100644
--- a/src/northbridge/intel/sandybridge/acpi.c
+++ b/src/northbridge/intel/sandybridge/acpi.c
@@ -121,7 +121,7 @@ static int init_opregion_vbt(igd_opregion_t *opregion)
optionrom_vbt_t *vbt = (optionrom_vbt_t *)(vbios +
oprom->vbt_offset);
- if (read32((unsigned long)vbt->hdr_signature) != VBT_SIGNATURE) {
+ if (read32(vbt->hdr_signature) != VBT_SIGNATURE) {
printk(BIOS_DEBUG, "VBT not found!\n");
return 1;
}
diff --git a/src/northbridge/intel/sandybridge/early_init.c b/src/northbridge/intel/sandybridge/early_init.c
index 3156f8662..d9ebe36dc 100644
--- a/src/northbridge/intel/sandybridge/early_init.c
+++ b/src/northbridge/intel/sandybridge/early_init.c
@@ -32,7 +32,7 @@ static void sandybridge_setup_bars(void)
{
/* Setting up Southbridge. In the northbridge code. */
printk(BIOS_DEBUG, "Setting up static southbridge registers...");
- pci_write_config32(PCI_DEV(0, 0x1f, 0), RCBA, DEFAULT_RCBA | 1);
+ pci_write_config32(PCI_DEV(0, 0x1f, 0), RCBA, (uintptr_t)DEFAULT_RCBA | 1);
pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, DEFAULT_PMBASE | 1);
pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44 /* ACPI_CNTL */ , 0x80); /* Enable ACPI BAR */
@@ -48,10 +48,10 @@ static void sandybridge_setup_bars(void)
/* Set up all hardcoded northbridge BARs */
pci_write_config32(PCI_DEV(0, 0x00, 0), EPBAR, DEFAULT_EPBAR | 1);
pci_write_config32(PCI_DEV(0, 0x00, 0), EPBAR + 4, (0LL+DEFAULT_EPBAR) >> 32);
- pci_write_config32(PCI_DEV(0, 0x00, 0), MCHBAR, DEFAULT_MCHBAR | 1);
- pci_write_config32(PCI_DEV(0, 0x00, 0), MCHBAR + 4, (0LL+DEFAULT_MCHBAR) >> 32);
- pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR, DEFAULT_DMIBAR | 1);
- pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR + 4, (0LL+DEFAULT_DMIBAR) >> 32);
+ pci_write_config32(PCI_DEV(0, 0x00, 0), MCHBAR, (uintptr_t)DEFAULT_MCHBAR | 1);
+ pci_write_config32(PCI_DEV(0, 0x00, 0), MCHBAR + 4, (0LL+(uintptr_t)DEFAULT_MCHBAR) >> 32);
+ pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR, (uintptr_t)DEFAULT_DMIBAR | 1);
+ pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR + 4, (0LL+(uintptr_t)DEFAULT_DMIBAR) >> 32);
/* Set C0000-FFFFF to access RAM on both reads and writes */
pci_write_config8(PCI_DEV(0, 0x00, 0), PAM0, 0x30);
diff --git a/src/northbridge/intel/sandybridge/gma.c b/src/northbridge/intel/sandybridge/gma.c
index 247c72320..554c0a5ed 100644
--- a/src/northbridge/intel/sandybridge/gma.c
+++ b/src/northbridge/intel/sandybridge/gma.c
@@ -280,12 +280,12 @@ static struct resource *gtt_res = NULL;
u32 gtt_read(u32 reg)
{
- return read32(gtt_res->base + reg);
+ return read32(res2mmio(gtt_res, reg, 0));
}
void gtt_write(u32 reg, u32 data)
{
- write32(gtt_res->base + reg, data);
+ write32(res2mmio(gtt_res, reg, 0), data);
}
static inline void gtt_write_powermeter(const struct gt_powermeter *pm)
@@ -588,10 +588,11 @@ static void gma_func0_init(struct device *dev)
#if CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT
/* This should probably run before post VBIOS init. */
printk(BIOS_SPEW, "Initializing VGA without OPROM.\n");
- u32 iobase, mmiobase, physbase, graphics_base;
+ u8 *mmiobase;
+ u32 iobase, physbase, graphics_base;
struct northbridge_intel_sandybridge_config *conf = dev->chip_info;
iobase = dev->resource_list[2].base;
- mmiobase = dev->resource_list[0].base;
+ mmiobase = res2mmio(&dev->resource_list[0], 0, 0);
physbase = pci_read_config32(dev, 0x5c) & ~0xf;
graphics_base = dev->resource_list[1].base;
diff --git a/src/northbridge/intel/sandybridge/gma.h b/src/northbridge/intel/sandybridge/gma.h
index 3a73e08c3..9854f21d2 100644
--- a/src/northbridge/intel/sandybridge/gma.h
+++ b/src/northbridge/intel/sandybridge/gma.h
@@ -117,4 +117,4 @@ typedef struct {
struct i915_gpu_controller_info;
int i915lightup_sandy(const struct i915_gpu_controller_info *info,
- u32 physbase, u16 pio, u32 mmio, u32 lfb);
+ u32 physbase, u16 pio, u8 *mmio, u32 lfb);
diff --git a/src/northbridge/intel/sandybridge/gma_ivybridge_lvds.c b/src/northbridge/intel/sandybridge/gma_ivybridge_lvds.c
index e3e1f4bd5..6c1295a73 100644
--- a/src/northbridge/intel/sandybridge/gma_ivybridge_lvds.c
+++ b/src/northbridge/intel/sandybridge/gma_ivybridge_lvds.c
@@ -36,7 +36,7 @@
#if IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT)
-static void link_train(u32 mmio)
+static void link_train(u8 *mmio)
{
write32(mmio+0xf000c,0x40);
write32(mmio+0x60100,0x40000);
@@ -54,7 +54,7 @@ static void link_train(u32 mmio)
write32(mmio+0x70008,0x80000050);
}
-static void link_normal_operation(u32 mmio)
+static void link_normal_operation(u8 *mmio)
{
write32(mmio + FDI_TX_CTL(0), 0x80044f02);
write32(mmio + FDI_RX_CTL(0),
@@ -62,7 +62,7 @@ static void link_normal_operation(u32 mmio)
| 0x2f50);
}
-static void enable_port(u32 mmio)
+static void enable_port(u8 *mmio)
{
write32(mmio + 0xec008, 0x2c010000);
write32(mmio + 0xec020, 0x2c010000);
@@ -160,7 +160,7 @@ static void enable_port(u32 mmio)
}
int i915lightup_sandy(const struct i915_gpu_controller_info *info,
- u32 physbase, u16 piobase, u32 mmio, u32 lfb)
+ u32 physbase, u16 piobase, u8 *mmio, u32 lfb)
{
int i;
u8 edid_data[128];
diff --git a/src/northbridge/intel/sandybridge/gma_sandybridge_lvds.c b/src/northbridge/intel/sandybridge/gma_sandybridge_lvds.c
index 08cceea38..eb86c6228 100644
--- a/src/northbridge/intel/sandybridge/gma_sandybridge_lvds.c
+++ b/src/northbridge/intel/sandybridge/gma_sandybridge_lvds.c
@@ -35,7 +35,7 @@
#if IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT)
-static void train_link(u32 mmio)
+static void train_link(u8 *mmio)
{
/* Clear interrupts. */
write32(mmio + DEIIR, 0xffffffff);
@@ -68,7 +68,7 @@ static void train_link(u32 mmio)
read32(mmio + 0x000f0014); // = 0x00000600
}
-static void power_port(u32 mmio)
+static void power_port(u8 *mmio)
{
read32(mmio + 0x000e1100); // = 0x00000000
write32(mmio + 0x000e1100, 0x00000000);
@@ -123,7 +123,7 @@ static void power_port(u32 mmio)
}
int i915lightup_sandy(const struct i915_gpu_controller_info *info,
- u32 physbase, u16 piobase, u32 mmio, u32 lfb)
+ u32 physbase, u16 piobase, u8 *mmio, u32 lfb)
{
int i;
u8 edid_data[128];
diff --git a/src/northbridge/intel/sandybridge/raminit_native.c b/src/northbridge/intel/sandybridge/raminit_native.c
index de6dac7a2..e892caada 100644
--- a/src/northbridge/intel/sandybridge/raminit_native.c
+++ b/src/northbridge/intel/sandybridge/raminit_native.c
@@ -181,10 +181,10 @@ static void wait_txt_clear(void)
if (!(cp.ecx & 0x40))
return;
/* Some TXT public bit. */
- if (!(read32(0xfed30010) & 1))
+ if (!(read32((void *)0xfed30010) & 1))
return;
/* Wait for TXT clear. */
- while (!(read8(0xfed40000) & (1 << 7))) ;
+ while (!(read8((void *)0xfed40000) & (1 << 7))) ;
}
static void sfence(void)
@@ -1105,7 +1105,7 @@ static void dram_ioregs(ramctr_timing * ctrl)
static void wait_428c(int channel)
{
while (1) {
- if (read32(DEFAULT_MCHBAR | 0x428c | (channel << 10)) & 0x50)
+ if (read32(DEFAULT_MCHBAR + 0x428c + (channel << 10)) & 0x50)
return;
}
}
@@ -2081,7 +2081,7 @@ static void fill_pattern0(ramctr_timing * ctrl, int channel, u32 a, u32 b)
get_precedening_channels(ctrl, channel) * 0x40;
printram("channel_offset=%x\n", channel_offset);
for (j = 0; j < 16; j++)
- write32(0x04000000 + channel_offset + 4 * j, j & 2 ? b : a);
+ write32((void *)(0x04000000 + channel_offset + 4 * j), j & 2 ? b : a);
sfence();
}
@@ -2100,9 +2100,9 @@ static void fill_pattern1(ramctr_timing * ctrl, int channel)
get_precedening_channels(ctrl, channel) * 0x40;
unsigned channel_step = 0x40 * num_of_channels(ctrl);
for (j = 0; j < 16; j++)
- write32(0x04000000 + channel_offset + j * 4, 0xffffffff);
+ write32((void *)(0x04000000 + channel_offset + j * 4), 0xffffffff);
for (j = 0; j < 16; j++)
- write32(0x04000000 + channel_offset + channel_step + j * 4, 0);
+ write32((void *)(0x04000000 + channel_offset + channel_step + j * 4), 0);
sfence();
}
@@ -2298,7 +2298,7 @@ static void adjust_high_timB(ramctr_timing * ctrl)
write32(DEFAULT_MCHBAR + 0x3400, 0x200);
FOR_ALL_POPULATED_CHANNELS {
fill_pattern1(ctrl, channel);
- write32(DEFAULT_MCHBAR | 0x4288 | (channel << 10), 1);
+ write32(DEFAULT_MCHBAR + 0x4288 + (channel << 10), 1);
}
FOR_ALL_POPULATED_CHANNELS FOR_ALL_POPULATED_RANKS {
@@ -2489,7 +2489,7 @@ static void write_training(ramctr_timing * ctrl)
FOR_ALL_POPULATED_CHANNELS {
fill_pattern0(ctrl, channel, 0xaaaaaaaa, 0x55555555);
- write32(DEFAULT_MCHBAR | 0x4288 | (channel << 10), 0);
+ write32(DEFAULT_MCHBAR + 0x4288 + (channel << 10), 0);
}
FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS
@@ -2602,16 +2602,16 @@ static void fill_pattern5(ramctr_timing * ctrl, int channel, int patno)
u32 val = use_base[patno - 1][i] & (1 << (j / 2)) ? base : 0;
if (invert[patno - 1][i] & (1 << (j / 2)))
val = ~val;
- write32(0x04000000 + channel_offset + i * channel_step +
- j * 4, val);
+ write32((void *)(0x04000000 + channel_offset + i * channel_step +
+ j * 4), val);
}
}
} else {
for (i = 0; i < sizeof(pattern) / sizeof(pattern[0]); i++) {
for (j = 0; j < 16; j++)
- write32(0x04000000 + channel_offset + i * channel_step +
- j * 4, pattern[i][j]);
+ write32((void *)(0x04000000 + channel_offset + i * channel_step +
+ j * 4), pattern[i][j]);
}
sfence();
}
@@ -2866,7 +2866,7 @@ static void discover_edges(ramctr_timing * ctrl)
FOR_ALL_POPULATED_CHANNELS {
fill_pattern0(ctrl, channel, 0, 0);
- write32(DEFAULT_MCHBAR | 0x4288 | (channel << 10), 0);
+ write32(DEFAULT_MCHBAR + 0x4288 + (channel << 10), 0);
FOR_ALL_LANES {
read32(DEFAULT_MCHBAR + 0x400 * channel +
lane * 4 + 0x4140);
@@ -2978,7 +2978,7 @@ static void discover_edges(ramctr_timing * ctrl)
}
fill_pattern0(ctrl, channel, 0, 0xffffffff);
- write32(DEFAULT_MCHBAR | 0x4288 | (channel << 10), 0);
+ write32(DEFAULT_MCHBAR + 0x4288 + (channel << 10), 0);
}
/* FIXME: under some conditions (older chipsets?) vendor BIOS sets both edges to the same value. */
@@ -3335,9 +3335,9 @@ static void write_controller_mr(ramctr_timing * ctrl)
int channel, slotrank;
FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS {
- write32(DEFAULT_MCHBAR | 0x0004 | (channel << 8) |
+ write32(DEFAULT_MCHBAR + 0x0004 + (channel << 8) +
lane_registers[slotrank], make_mr0(ctrl, slotrank));
- write32(DEFAULT_MCHBAR | 0x0008 | (channel << 8) |
+ write32(DEFAULT_MCHBAR + 0x0008 + (channel << 8) +
lane_registers[slotrank], make_mr1(ctrl, slotrank));
}
}
@@ -3347,46 +3347,46 @@ static void channel_test(ramctr_timing * ctrl)
int channel, slotrank, lane;
FOR_ALL_POPULATED_CHANNELS
- if (read32(DEFAULT_MCHBAR | 0x42a0 | (channel << 10)) & 0xa000)
+ if (read32(DEFAULT_MCHBAR + 0x42a0 + (channel << 10)) & 0xa000)
die("Mini channel test failed (1)\n");
FOR_ALL_POPULATED_CHANNELS {
fill_pattern0(ctrl, channel, 0x12345678, 0x98765432);
- write32(DEFAULT_MCHBAR | 0x4288 | (channel << 10), 0);
+ write32(DEFAULT_MCHBAR + 0x4288 + (channel << 10), 0);
}
for (slotrank = 0; slotrank < 4; slotrank++)
FOR_ALL_CHANNELS
if (ctrl->rankmap[channel] & (1 << slotrank)) {
FOR_ALL_LANES {
- write32(DEFAULT_MCHBAR | (0x4f40 + 4 * lane), 0);
- write32(DEFAULT_MCHBAR | (0x4d40 + 4 * lane), 0);
+ write32(DEFAULT_MCHBAR + (0x4f40 + 4 * lane), 0);
+ write32(DEFAULT_MCHBAR + (0x4d40 + 4 * lane), 0);
}
wait_428c(channel);
- write32(DEFAULT_MCHBAR | 0x4220 | (channel << 10), 0x0001f006);
- write32(DEFAULT_MCHBAR | 0x4230 | (channel << 10), 0x0028a004);
- write32(DEFAULT_MCHBAR | 0x4200 | (channel << 10),
+ write32(DEFAULT_MCHBAR + 0x4220 + (channel << 10), 0x0001f006);
+ write32(DEFAULT_MCHBAR + 0x4230 + (channel << 10), 0x0028a004);
+ write32(DEFAULT_MCHBAR + 0x4200 + (channel << 10),
0x00060000 | (slotrank << 24));
- write32(DEFAULT_MCHBAR | 0x4210 | (channel << 10), 0x00000244);
- write32(DEFAULT_MCHBAR | 0x4224 | (channel << 10), 0x0001f201);
- write32(DEFAULT_MCHBAR | 0x4234 | (channel << 10), 0x08281064);
- write32(DEFAULT_MCHBAR | 0x4204 | (channel << 10),
+ write32(DEFAULT_MCHBAR + 0x4210 + (channel << 10), 0x00000244);
+ write32(DEFAULT_MCHBAR + 0x4224 + (channel << 10), 0x0001f201);
+ write32(DEFAULT_MCHBAR + 0x4234 + (channel << 10), 0x08281064);
+ write32(DEFAULT_MCHBAR + 0x4204 + (channel << 10),
0x00000000 | (slotrank << 24));
- write32(DEFAULT_MCHBAR | 0x4214 | (channel << 10), 0x00000242);
- write32(DEFAULT_MCHBAR | 0x4228 | (channel << 10), 0x0001f105);
- write32(DEFAULT_MCHBAR | 0x4238 | (channel << 10), 0x04281064);
- write32(DEFAULT_MCHBAR | 0x4208 | (channel << 10),
+ write32(DEFAULT_MCHBAR + 0x4214 + (channel << 10), 0x00000242);
+ write32(DEFAULT_MCHBAR + 0x4228 + (channel << 10), 0x0001f105);
+ write32(DEFAULT_MCHBAR + 0x4238 + (channel << 10), 0x04281064);
+ write32(DEFAULT_MCHBAR + 0x4208 + (channel << 10),
0x00000000 | (slotrank << 24));
- write32(DEFAULT_MCHBAR | 0x4218 | (channel << 10), 0x00000242);
- write32(DEFAULT_MCHBAR | 0x422c | (channel << 10), 0x0001f002);
- write32(DEFAULT_MCHBAR | 0x423c | (channel << 10), 0x00280c01);
- write32(DEFAULT_MCHBAR | 0x420c | (channel << 10),
+ write32(DEFAULT_MCHBAR + 0x4218 + (channel << 10), 0x00000242);
+ write32(DEFAULT_MCHBAR + 0x422c + (channel << 10), 0x0001f002);
+ write32(DEFAULT_MCHBAR + 0x423c + (channel << 10), 0x00280c01);
+ write32(DEFAULT_MCHBAR + 0x420c + (channel << 10),
0x00060400 | (slotrank << 24));
- write32(DEFAULT_MCHBAR | 0x421c | (channel << 10), 0x00000240);
- write32(DEFAULT_MCHBAR | 0x4284 | (channel << 10), 0x000c0001);
+ write32(DEFAULT_MCHBAR + 0x421c + (channel << 10), 0x00000240);
+ write32(DEFAULT_MCHBAR + 0x4284 + (channel << 10), 0x000c0001);
wait_428c(channel);
FOR_ALL_LANES
- if (read32(DEFAULT_MCHBAR | 0x4340 | (channel << 10)))
+ if (read32(DEFAULT_MCHBAR + 0x4340 + (channel << 10)))
die("Mini channel test failed (2)\n");
}
}
@@ -3403,9 +3403,9 @@ static void set_scrambling_seed(ramctr_timing * ctrl)
};
FOR_ALL_POPULATED_CHANNELS {
MCHBAR32(0x4020 + 0x400 * channel) &= ~0x10000000;
- write32(DEFAULT_MCHBAR | 0x4034, seeds[channel][0]);
- write32(DEFAULT_MCHBAR | 0x403c, seeds[channel][1]);
- write32(DEFAULT_MCHBAR | 0x4038, seeds[channel][2]);
+ write32(DEFAULT_MCHBAR + 0x4034, seeds[channel][0]);
+ write32(DEFAULT_MCHBAR + 0x403c, seeds[channel][1]);
+ write32(DEFAULT_MCHBAR + 0x4038, seeds[channel][2]);
}
}
@@ -3463,12 +3463,12 @@ static void set_4008c(ramctr_timing * ctrl)
else
b4_8_12 = 0x2220;
- reg = read32(DEFAULT_MCHBAR | 0x400c | (channel << 10));
- write32(DEFAULT_MCHBAR | 0x400c | (channel << 10),
+ reg = read32(DEFAULT_MCHBAR + 0x400c + (channel << 10));
+ write32(DEFAULT_MCHBAR + 0x400c + (channel << 10),
(reg & 0xFFF0FFFF)
| (ctrl->ref_card_offset[channel] << 16)
| (ctrl->ref_card_offset[channel] << 18));
- write32(DEFAULT_MCHBAR | 0x4008 | (channel << 10),
+ write32(DEFAULT_MCHBAR + 0x4008 + (channel << 10),
0x0a000000
| (b20 << 20)
| ((ctrl->ref_card_offset[channel] + 2) << 16)
@@ -3480,7 +3480,7 @@ static void set_42a0(ramctr_timing * ctrl)
{
int channel;
FOR_ALL_POPULATED_CHANNELS {
- write32(DEFAULT_MCHBAR | (0x42a0 + 0x400 * channel),
+ write32(DEFAULT_MCHBAR + (0x42a0 + 0x400 * channel),
0x00001000 | ctrl->rankmap[channel]);
MCHBAR32(0x4004 + 0x400 * channel) &= ~0x20000000; // OK
}
@@ -3499,15 +3499,15 @@ static void final_registers(ramctr_timing * ctrl)
int t3_ns;
u32 r32;
- write32(DEFAULT_MCHBAR | 0x4cd4, 0x00000046);
+ write32(DEFAULT_MCHBAR + 0x4cd4, 0x00000046);
- write32(DEFAULT_MCHBAR | 0x400c, (read32(DEFAULT_MCHBAR | 0x400c) & 0xFFFFCFFF) | 0x1000); // OK
- write32(DEFAULT_MCHBAR | 0x440c, (read32(DEFAULT_MCHBAR | 0x440c) & 0xFFFFCFFF) | 0x1000); // OK
- write32(DEFAULT_MCHBAR | 0x4cb0, 0x00000740);
- write32(DEFAULT_MCHBAR | 0x4380, 0x00000aaa); // OK
- write32(DEFAULT_MCHBAR | 0x4780, 0x00000aaa); // OK
- write32(DEFAULT_MCHBAR | 0x4f88, 0x5f7003ff); // OK
- write32(DEFAULT_MCHBAR | 0x5064, 0x00073000 | ctrl->reg_5064b0); // OK
+ write32(DEFAULT_MCHBAR + 0x400c, (read32(DEFAULT_MCHBAR + 0x400c) & 0xFFFFCFFF) | 0x1000); // OK
+ write32(DEFAULT_MCHBAR + 0x440c, (read32(DEFAULT_MCHBAR + 0x440c) & 0xFFFFCFFF) | 0x1000); // OK
+ write32(DEFAULT_MCHBAR + 0x4cb0, 0x00000740);
+ write32(DEFAULT_MCHBAR + 0x4380, 0x00000aaa); // OK
+ write32(DEFAULT_MCHBAR + 0x4780, 0x00000aaa); // OK
+ write32(DEFAULT_MCHBAR + 0x4f88, 0x5f7003ff); // OK
+ write32(DEFAULT_MCHBAR + 0x5064, 0x00073000 | ctrl->reg_5064b0); // OK
FOR_ALL_CHANNELS {
switch (ctrl->rankmap[channel]) {
@@ -3528,15 +3528,15 @@ static void final_registers(ramctr_timing * ctrl)
}
}
- write32 (DEFAULT_MCHBAR | 0x5880, 0xca9171e5);
- write32 (DEFAULT_MCHBAR | 0x5888,
- (read32 (DEFAULT_MCHBAR | 0x5888) & ~0xffffff) | 0xe4d5d0);
- write32 (DEFAULT_MCHBAR | 0x58a8, read32 (DEFAULT_MCHBAR | 0x58a8) & ~0x1f);
- write32 (DEFAULT_MCHBAR | 0x4294,
- (read32 (DEFAULT_MCHBAR | 0x4294) & ~0x30000)
+ write32 (DEFAULT_MCHBAR + 0x5880, 0xca9171e5);
+ write32 (DEFAULT_MCHBAR + 0x5888,
+ (read32 (DEFAULT_MCHBAR + 0x5888) & ~0xffffff) | 0xe4d5d0);
+ write32 (DEFAULT_MCHBAR + 0x58a8, read32 (DEFAULT_MCHBAR + 0x58a8) & ~0x1f);
+ write32 (DEFAULT_MCHBAR + 0x4294,
+ (read32 (DEFAULT_MCHBAR + 0x4294) & ~0x30000)
| (1 << 16));
- write32 (DEFAULT_MCHBAR | 0x4694,
- (read32 (DEFAULT_MCHBAR | 0x4694) & ~0x30000)
+ write32 (DEFAULT_MCHBAR + 0x4694,
+ (read32 (DEFAULT_MCHBAR + 0x4694) & ~0x30000)
| (1 << 16));
MCHBAR32(0x5030) |= 1; // OK
@@ -3721,10 +3721,10 @@ void init_dram_ddr3(spd_raw_data * spds, int mobile, int min_tck,
wrmsr(0x000002e6, (msr_t) { .lo = 0, .hi = 0 });
- reg_5d10 = read32(DEFAULT_MCHBAR | 0x5d10); // !!! = 0x00000000
+ reg_5d10 = read32(DEFAULT_MCHBAR + 0x5d10); // !!! = 0x00000000
if ((pcie_read_config16(SOUTHBRIDGE, 0xa2) & 0xa0) == 0x20 /* 0x0004 */
&& reg_5d10 && !s3resume) {
- write32(DEFAULT_MCHBAR | 0x5d10, 0);
+ write32(DEFAULT_MCHBAR + 0x5d10, 0);
/* Need reset. */
outb(0x6, 0xcf9);
@@ -3858,7 +3858,7 @@ void init_dram_ddr3(spd_raw_data * spds, int mobile, int min_tck,
}
/* FIXME: should be hardware revision-dependent. */
- write32(DEFAULT_MCHBAR | 0x5024, 0x00a030ce);
+ write32(DEFAULT_MCHBAR + 0x5024, 0x00a030ce);
set_scrambling_seed(&ctrl);
diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h
index 0790ae8fd..ab9557265 100644
--- a/src/northbridge/intel/sandybridge/sandybridge.h
+++ b/src/northbridge/intel/sandybridge/sandybridge.h
@@ -48,10 +48,15 @@
/* Northbridge BARs */
#define DEFAULT_PCIEXBAR CONFIG_MMCONF_BASE_ADDRESS /* 4 KB per PCIe device */
+#ifndef __ACPI__
+#define DEFAULT_MCHBAR ((u8 *)0xfed10000) /* 16 KB */
+#define DEFAULT_DMIBAR ((u8 *)0xfed18000) /* 4 KB */
+#else
#define DEFAULT_MCHBAR 0xfed10000 /* 16 KB */
#define DEFAULT_DMIBAR 0xfed18000 /* 4 KB */
+#endif
#define DEFAULT_EPBAR 0xfed19000 /* 4 KB */
-#define DEFAULT_RCBABASE 0xfed1c000
+#define DEFAULT_RCBABASE ((u8 *)0xfed1c000)
#include <southbridge/intel/bd82x6x/pch.h>
diff --git a/src/northbridge/intel/sch/early_init.c b/src/northbridge/intel/sch/early_init.c
index d80cc215d..0c206bd6c 100644
--- a/src/northbridge/intel/sch/early_init.c
+++ b/src/northbridge/intel/sch/early_init.c
@@ -205,7 +205,8 @@ static void sch_setup_non_standard_bars(void)
sch_port_access_write(2, 9, 4, DEFAULT_PCIEXBAR | 1); /* b1+ */
/* RCBA */
- pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xF0, (DEFAULT_RCBABASE | 1));
+ pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xF0,
+ ((uintptr_t)DEFAULT_RCBABASE | 1));
printk(BIOS_DEBUG, " done.\n");
}
diff --git a/src/northbridge/intel/sch/sch.h b/src/northbridge/intel/sch/sch.h
index 3eb082585..9ac79ea8d 100644
--- a/src/northbridge/intel/sch/sch.h
+++ b/src/northbridge/intel/sch/sch.h
@@ -36,7 +36,7 @@ void sch_port_access_write_ram_cmd(int cmd, int port, int reg, int data);
#define DEFAULT_GPE0BASE 0x5C0
#define DEFAULT_SMMCNTRLBASE 0x3F703F76
-#define DEFAULT_RCBABASE 0xfed1c000
+#define DEFAULT_RCBABASE ((u8 *)0xfed1c000)
#define DEFAULT_PCIEXBAR CONFIG_MMCONF_BASE_ADDRESS /* 4 KB per PCIe device */
diff --git a/src/northbridge/via/cn700/raminit.c b/src/northbridge/via/cn700/raminit.c
index 747cbfd92..289b31515 100644
--- a/src/northbridge/via/cn700/raminit.c
+++ b/src/northbridge/via/cn700/raminit.c
@@ -393,7 +393,7 @@ static void sdram_set_post(const struct mem_controller *ctrl)
pci_write_config16(dev, 0xa4, 0x0010);
}
-static void sdram_enable(device_t dev, unsigned long rank_address)
+static void sdram_enable(device_t dev, u8 *rank_address)
{
u8 i;
@@ -413,7 +413,7 @@ static void sdram_enable(device_t dev, unsigned long rank_address)
PRINT_DEBUG_MEM("RAM Enable 3: Mode register set\n");
do_ram_command(dev, RAM_COMMAND_MRS);
read32(rank_address + 0x120000); /* EMRS DLL Enable */
- read32(rank_address + 0x800); /* MRS DLL Reset */
+ read32(rank_address + 0x800); /* MRS DLL Reset */
/* 4. Precharge all again. */
PRINT_DEBUG_MEM("RAM Enable 4: Precharge all\n");
@@ -457,10 +457,10 @@ static void ddr_ram_setup(const struct mem_controller *ctrl)
c7_cpu_setup(ctrl->d0f2);
sdram_set_registers(ctrl);
sdram_set_size(ctrl);
- sdram_enable(ctrl->d0f3, 0);
+ sdram_enable(ctrl->d0f3, (u8 *)0);
reg = pci_read_config8(ctrl->d0f3, 0x41);
if (reg != 0)
sdram_enable(ctrl->d0f3,
- pci_read_config8(ctrl->d0f3, 0x40) << 26);
+ (u8 *)(pci_read_config8(ctrl->d0f3, 0x40) << 26));
sdram_set_post(ctrl);
}
diff --git a/src/northbridge/via/cx700/lpc.c b/src/northbridge/via/cx700/lpc.c
index 1e6d2ce47..56842b094 100644
--- a/src/northbridge/via/cx700/lpc.c
+++ b/src/northbridge/via/cx700/lpc.c
@@ -274,7 +274,7 @@ static void cx700_lpc_init(struct device *dev)
#if CONFIG_IOAPIC
#define IO_APIC_ID 2
- setup_ioapic(IO_APIC_ADDR, IO_APIC_ID);
+ setup_ioapic(VIO_APIC_VADDR, IO_APIC_ID);
#endif
/* Initialize interrupts */
diff --git a/src/northbridge/via/cx700/raminit.c b/src/northbridge/via/cx700/raminit.c
index 32be1ea4c..fabd7ffb3 100644
--- a/src/northbridge/via/cx700/raminit.c
+++ b/src/northbridge/via/cx700/raminit.c
@@ -967,9 +967,9 @@ static void step_20_21(const struct mem_controller *ctrl)
val = pci_read_config8(PCI_DEV(0, 0, 4), SCRATCH_DRAM_NB_ODT);
if (val & DDR2_ODT_150ohm)
- read32(0x102200);
+ read32((void *)0x102200);
else
- read32(0x102020);
+ read32((void *)0x102020);
/* Step 21. Normal operation */
printk(BIOS_SPEW, "RAM Enable 5: Normal operation\n");
@@ -995,7 +995,7 @@ static void step_2_19(const struct mem_controller *ctrl)
// Step 4
printk(BIOS_SPEW, "SEND: ");
- read32(0);
+ read32((void *)0);
printk(BIOS_SPEW, "OK\n");
// Step 5
@@ -1007,7 +1007,7 @@ static void step_2_19(const struct mem_controller *ctrl)
// Step 7
printk(BIOS_SPEW, "SEND: ");
- read32(0);
+ read32((void *)0);
printk(BIOS_SPEW, "OK\n");
/* Step 8. Mode register set. */
@@ -1019,14 +1019,14 @@ static void step_2_19(const struct mem_controller *ctrl)
val = pci_read_config8(PCI_DEV(0, 0, 4), SCRATCH_DRAM_NB_ODT);
if (val & DDR2_ODT_150ohm)
- read32(0x102200); //DDR2_ODT_150ohm
+ read32((void *)0x102200); //DDR2_ODT_150ohm
else
- read32(0x102020);
+ read32((void *)0x102020);
printk(BIOS_SPEW, "OK\n");
// Step 10
printk(BIOS_SPEW, "SEND: ");
- read32(0x800);
+ read32((void *)0x800);
printk(BIOS_SPEW, "OK\n");
/* Step 11. Precharge all. Wait tRP. */
@@ -1035,7 +1035,7 @@ static void step_2_19(const struct mem_controller *ctrl)
// Step 12
printk(BIOS_SPEW, "SEND: ");
- read32(0x0);
+ read32((u32 *)0x0);
printk(BIOS_SPEW, "OK\n");
/* Step 13. Perform 8 refresh cycles. Wait tRC each time. */
@@ -1046,7 +1046,7 @@ static void step_2_19(const struct mem_controller *ctrl)
// Step 16: Repeat Step 14 and 15 another 7 times
for (i = 0; i < 8; i++) {
// Step 14
- read32(0);
+ read32((u32 *)0);
printk(BIOS_SPEW, ".");
// Step 15
@@ -1076,7 +1076,7 @@ static void step_2_19(const struct mem_controller *ctrl)
val = pci_read_config8(MEMCTRL, 0x61);
val = val >> 6;
i |= DDR2_Twr_table[val];
- read32(i);
+ read32((void *)i);
printk(BIOS_DEBUG, "MRS = %08x\n", i);
@@ -1085,9 +1085,9 @@ static void step_2_19(const struct mem_controller *ctrl)
// Step 19
val = pci_read_config8(PCI_DEV(0, 0, 4), SCRATCH_DRAM_NB_ODT);
if (val & DDR2_ODT_150ohm)
- read32(0x103e00); //EMRS OCD Default
+ read32((void *)0x103e00); //EMRS OCD Default
else
- read32(0x103c20);
+ read32((void *)0x103c20);
}
static void sdram_set_vr(const struct mem_controller *ctrl, u8 num)
@@ -1133,45 +1133,45 @@ static void sdram_calc_size(const struct mem_controller *ctrl, u8 num)
u8 ca, ra, ba, reg;
ba = pci_read_config8(PCI_DEV(0, 0, 4), SCRATCH_FLAGS);
if (ba == 8) {
- write8(0, 0x0d);
- ra = read8(0);
- write8((1 << SDRAM1X_RA_12_8bk), 0x0c);
- ra = read8(0);
-
- write8(0, 0x0a);
- ca = read8(0);
- write8((1 << SDRAM1X_CA_09_8bk), 0x0c);
- ca = read8(0);
-
- write8(0, 0x03);
- ba = read8(0);
- write8((1 << SDRAM1X_BA2_8bk), 0x02);
- ba = read8(0);
- write8((1 << SDRAM1X_BA1_8bk), 0x01);
- ba = read8(0);
+ write8((void *)0, 0x0d);
+ ra = read8((void *)0);
+ write8((void *)(1 << SDRAM1X_RA_12_8bk), 0x0c);
+ ra = read8((void *)0);
+
+ write8((void *)0, 0x0a);
+ ca = read8((void *)0);
+ write8((void *)(1 << SDRAM1X_CA_09_8bk), 0x0c);
+ ca = read8((void *)0);
+
+ write8((void *)0, 0x03);
+ ba = read8((void *)0);
+ write8((void *)(1 << SDRAM1X_BA2_8bk), 0x02);
+ ba = read8((void *)0);
+ write8((void *)(1 << SDRAM1X_BA1_8bk), 0x01);
+ ba = read8((void *)0);
} else {
- write8(0, 0x0f);
- ra = read8(0);
- write8((1 << SDRAM1X_RA_14), 0x0e);
- ra = read8(0);
- write8((1 << SDRAM1X_RA_13), 0x0d);
- ra = read8(0);
- write8((1 << SDRAM1X_RA_12), 0x0c);
- ra = read8(0);
-
- write8(0, 0x0c);
- ca = read8(0);
- write8((1 << SDRAM1X_CA_12), 0x0b);
- ca = read8(0);
- write8((1 << SDRAM1X_CA_11), 0x0a);
- ca = read8(0);
- write8((1 << SDRAM1X_CA_09), 0x09);
- ca = read8(0);
-
- write8(0, 0x02);
- ba = read8(0);
- write8((1 << SDRAM1X_BA1), 0x01);
- ba = read8(0);
+ write8((void *)0, 0x0f);
+ ra = read8((void *)0);
+ write8((void *)(1 << SDRAM1X_RA_14), 0x0e);
+ ra = read8((void *)0);
+ write8((void *)(1 << SDRAM1X_RA_13), 0x0d);
+ ra = read8((void *)0);
+ write8((void *)(1 << SDRAM1X_RA_12), 0x0c);
+ ra = read8((void *)0);
+
+ write8((void *)0, 0x0c);
+ ca = read8((void *)0);
+ write8((void *)(1 << SDRAM1X_CA_12), 0x0b);
+ ca = read8((void *)0);
+ write8((void *)(1 << SDRAM1X_CA_11), 0x0a);
+ ca = read8((void *)0);
+ write8((void *)(1 << SDRAM1X_CA_09), 0x09);
+ ca = read8((void *)0);
+
+ write8((void *)0, 0x02);
+ ba = read8((void *)0);
+ write8((void *)(1 << SDRAM1X_BA1), 0x01);
+ ba = read8((void *)0);
}
if (ra < 10 || ra > 15)
@@ -1277,19 +1277,19 @@ static void sdram_enable(const struct mem_controller *ctrl)
if (reg8) {
sdram_set_vr(ctrl, i);
sdram_ending_addr(ctrl, i);
- write32(0, 0x55555555);
- write32(4, 0x55555555);
+ write32((void *)0, 0x55555555);
+ write32((void *)4, 0x55555555);
udelay(15);
- if (read32(0) != 0x55555555)
+ if (read32((void *)0) != 0x55555555)
break;
- if (read32(4) != 0x55555555)
+ if (read32((void *)4) != 0x55555555)
break;
- write32(0, 0xaaaaaaaa);
- write32(4, 0xaaaaaaaa);
+ write32((void *)0, 0xaaaaaaaa);
+ write32((void *)4, 0xaaaaaaaa);
udelay(15);
- if (read32(0) != 0xaaaaaaaa)
+ if (read32((void *)0) != 0xaaaaaaaa)
break;
- if (read32(4) != 0xaaaaaaaa)
+ if (read32((void *)4) != 0xaaaaaaaa)
break;
sdram_clear_vr_addr(ctrl, i);
}
@@ -1310,19 +1310,19 @@ static void sdram_enable(const struct mem_controller *ctrl)
sdram_set_vr(ctrl, i);
sdram_ending_addr(ctrl, i);
- write32(0, 0x55555555);
- write32(4, 0x55555555);
+ write32((void *)0, 0x55555555);
+ write32((void *)4, 0x55555555);
udelay(15);
- if (read32(0) != 0x55555555)
+ if (read32((void *)0) != 0x55555555)
break;
- if (read32(4) != 0x55555555)
+ if (read32((void *)4) != 0x55555555)
break;
- write32(0, 0xaaaaaaaa);
- write32(4, 0xaaaaaaaa);
+ write32((void *)0, 0xaaaaaaaa);
+ write32((void *)4, 0xaaaaaaaa);
udelay(15);
- if (read32(0) != 0xaaaaaaaa)
+ if (read32((void *)0) != 0xaaaaaaaa)
break;
- if (read32(4) != 0xaaaaaaaa)
+ if (read32((void *)4) != 0xaaaaaaaa)
break;
sdram_clear_vr_addr(ctrl, i);
}
@@ -1364,17 +1364,17 @@ static void sdram_enable(const struct mem_controller *ctrl)
sdram_set_vr(ctrl, i);
sdram_ending_addr(ctrl, i);
if (reg8 == 4) {
- write8(0, 0x02);
- val = read8(0);
- write8((1 << SDRAM1X_BA1), 0x01);
- val = read8(0);
+ write8((void *)0, 0x02);
+ val = read8((void *)0);
+ write8((void *)(1 << SDRAM1X_BA1), 0x01);
+ val = read8((void *)0);
} else {
- write8(0, 0x03);
- val = read8(0);
- write8((1 << SDRAM1X_BA2_8bk), 0x02);
- val = read8(0);
- write8((1 << SDRAM1X_BA1_8bk), 0x01);
- val = read8(0);
+ write8((void *)0, 0x03);
+ val = read8((void *)0);
+ write8((void *)(1 << SDRAM1X_BA2_8bk), 0x02);
+ val = read8((void *)0);
+ write8((void *)(1 << SDRAM1X_BA1_8bk), 0x01);
+ val = read8((void *)0);
}
if (val < dl)
dl = val;
diff --git a/src/northbridge/via/vx900/lpc.c b/src/northbridge/via/vx900/lpc.c
index 3cff6b0bf..61a8a7b96 100644
--- a/src/northbridge/via/vx900/lpc.c
+++ b/src/northbridge/via/vx900/lpc.c
@@ -139,10 +139,10 @@ static void vx900_lpc_ioapic_setup(device_t dev)
/* The base address of this IOAPIC _must_ be at 0xfec00000.
* Don't move this value to a #define, as people might think it's
* configurable. It is not. */
- const u32 base = config->base;
- if (base != 0xfec00000) {
+ const void *base = config->base;
+ if (base != (void *)0xfec00000) {
printk(BIOS_ERR, "ERROR: South module IOAPIC base should be at "
- "0xfec00000\n but we found it at 0x%.8x\n", base);
+ "0xfec00000\n but we found it at %p\n", base);
return;
}
diff --git a/src/northbridge/via/vx900/traf_ctrl.c b/src/northbridge/via/vx900/traf_ctrl.c
index 5183391c7..fb151935b 100644
--- a/src/northbridge/via/vx900/traf_ctrl.c
+++ b/src/northbridge/via/vx900/traf_ctrl.c
@@ -80,24 +80,24 @@ static void vx900_north_ioapic_setup(device_t dev)
* be between 0xfec00000 and 0xfecfff00
* be 256-byte aligned
*/
- if ((config->base < 0xfec0000 || config->base > 0xfecfff00)
- || ((config->base & 0xff) != 0)) {
+ if ((config->base < (void *)0xfec0000 || config->base > (void *)0xfecfff00)
+ || (((uintptr_t)config->base & 0xff) != 0)) {
printk(BIOS_ERR, "ERROR: North module IOAPIC base should be "
"between 0xfec00000 and 0xfecfff00\n"
"and must be aligned to a 256-byte boundary, "
- "but we found it at 0x%.8x\n", config->base);
+ "but we found it at 0x%p\n", config->base);
return;
}
printk(BIOS_DEBUG, "VX900 TRAF_CTR: Setting up the north module IOAPIC "
- "at 0%.8x\n", config->base);
+ "at %p\n", config->base);
/* First register of the IOAPIC base */
- base_val = (config->base >> 8) & 0xff;
+ base_val = (((uintptr_t)config->base) >> 8) & 0xff;
pci_write_config8(dev, 0x41, base_val);
/* Second register of the base.
* Bit[7] also enables the IOAPIC and bit[5] enables MSI cycles */
- base_val = (config->base >> 16) & 0xf;
+ base_val = (((uintptr_t)config->base) >> 16) & 0xf;
pci_mod_config8(dev, 0x40, 0, base_val | (1 << 7) | (1 << 5));
}