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authorKevin Paul Herbert <kph@meraki.net>2014-12-24 18:43:20 -0800
committerAlexandru Gagniuc <mr.nuke.me@gmail.com>2015-02-15 08:50:22 +0100
commitbde6d309dfafe58732ec46314a2d4c08974b62d4 (patch)
tree17ba00565487ddfbb5759c96adfbb3fffe2a4550 /src/northbridge/intel/gm45
parent4b10dec1a66122b515b2191f823d7fd379ec655f (diff)
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x86: Change MMIO addr in readN(addr)/writeN(addr, val) to pointer
On x86, change the type of the address parameter in read8()/read16/read32()/write8()/write16()/write32() to be a pointer, instead of unsigned long. Change-Id: Ic26dd8a72d82828b69be3c04944710681b7bd330 Signed-off-by: Kevin Paul Herbert <kph@meraki.net> Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/7784 Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/northbridge/intel/gm45')
-rw-r--r--src/northbridge/intel/gm45/early_init.c4
-rw-r--r--src/northbridge/intel/gm45/gm45.h7
-rw-r--r--src/northbridge/intel/gm45/gma.c10
-rw-r--r--src/northbridge/intel/gm45/pcie.c6
-rw-r--r--src/northbridge/intel/gm45/raminit.c12
-rw-r--r--src/northbridge/intel/gm45/raminit_read_write_training.c12
-rw-r--r--src/northbridge/intel/gm45/raminit_receive_enable_calibration.c2
7 files changed, 29 insertions, 24 deletions
diff --git a/src/northbridge/intel/gm45/early_init.c b/src/northbridge/intel/gm45/early_init.c
index 335ef6874..224dfcefe 100644
--- a/src/northbridge/intel/gm45/early_init.c
+++ b/src/northbridge/intel/gm45/early_init.c
@@ -26,10 +26,10 @@ void gm45_early_init(void)
const device_t d0f0 = PCI_DEV(0, 0, 0);
/* Setup MCHBAR. */
- pci_write_config32(d0f0, D0F0_MCHBAR_LO, DEFAULT_MCHBAR | 1);
+ pci_write_config32(d0f0, D0F0_MCHBAR_LO, (uintptr_t)DEFAULT_MCHBAR | 1);
/* Setup DMIBAR. */
- pci_write_config32(d0f0, D0F0_DMIBAR_LO, DEFAULT_DMIBAR | 1);
+ pci_write_config32(d0f0, D0F0_DMIBAR_LO, (uintptr_t)DEFAULT_DMIBAR | 1);
/* Setup EPBAR. */
pci_write_config32(d0f0, D0F0_EPBAR_LO, DEFAULT_EPBAR | 1);
diff --git a/src/northbridge/intel/gm45/gm45.h b/src/northbridge/intel/gm45/gm45.h
index 5bdf9e464..a31ea7da4 100644
--- a/src/northbridge/intel/gm45/gm45.h
+++ b/src/northbridge/intel/gm45/gm45.h
@@ -187,10 +187,15 @@ enum {
(could be reduced to 10 bytes) */
+#ifndef __ACPI__
+#define DEFAULT_MCHBAR ((u8 *)0xfed14000)
+#define DEFAULT_DMIBAR ((u8 *)0xfed18000)
+#else
#define DEFAULT_MCHBAR 0xfed14000
#define DEFAULT_DMIBAR 0xfed18000
+#endif
#define DEFAULT_EPBAR 0xfed19000
-#define DEFAULT_HECIBAR 0xfed1a000
+#define DEFAULT_HECIBAR ((u8 *)0xfed1a000)
/* 4 KB per PCIe device */
#define DEFAULT_PCIEXBAR CONFIG_MMCONF_BASE_ADDRESS
diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c
index 74e16ad2f..4cf277616 100644
--- a/src/northbridge/intel/gm45/gma.c
+++ b/src/northbridge/intel/gm45/gma.c
@@ -43,12 +43,12 @@ static struct resource *gtt_res = NULL;
void gtt_write(u32 reg, u32 data)
{
- write32(gtt_res->base + reg, data);
+ write32(res2mmio(gtt_res, reg, 0), data);
}
#if IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT)
-static void power_port(u32 mmio)
+static void power_port(u8 *mmio)
{
read32(mmio + 0x00061100); // = 0x00000000
write32(mmio + 0x00061100, 0x00000000);
@@ -103,7 +103,7 @@ static void power_port(u32 mmio)
}
static void intel_gma_init(const struct northbridge_intel_gm45_config *info,
- u32 mmio, u32 physbase, u16 piobase, u32 lfb)
+ u8 *mmio, u32 physbase, u16 piobase, u32 lfb)
{
int i;
@@ -464,8 +464,8 @@ static void gma_func0_init(struct device *dev)
&& lfb_res && lfb_res->base) {
printk(BIOS_SPEW, "Initializing VGA without OPROM. MMIO 0x%llx\n",
gtt_res->base);
- intel_gma_init(conf, gtt_res->base, physbase, pio_res->base,
- lfb_res->base);
+ intel_gma_init(conf, res2mmio(gtt_res, 0, 0), physbase,
+ pio_res->base, lfb_res->base);
}
/* Linux relies on VBT for panel info. */
diff --git a/src/northbridge/intel/gm45/pcie.c b/src/northbridge/intel/gm45/pcie.c
index 39791a62b..ae34a11b5 100644
--- a/src/northbridge/intel/gm45/pcie.c
+++ b/src/northbridge/intel/gm45/pcie.c
@@ -308,7 +308,7 @@ static void setup_rcrb(const int peg_enabled)
/* Link1: component ID 1, link valid. */
EPBAR32(EPLE1D) = (EPBAR32(EPLE1D) & 0xff000000) | (1 << 16) | (1 << 0);
- EPBAR32(EPLE1A) = DEFAULT_DMIBAR;
+ EPBAR32(EPLE1A) = (uintptr_t)DEFAULT_DMIBAR;
if (peg_enabled)
/* Link2: link_valid. */
@@ -322,12 +322,12 @@ static void setup_rcrb(const int peg_enabled)
/* Link1: target port 0, component id 2 (ICH), link valid. */
DMIBAR32(DMILE1D) = (0 << 24) | (2 << 16) | (1 << 0);
- DMIBAR32(DMILE1A) = DEFAULT_RCBA;
+ DMIBAR32(DMILE1A) = (uintptr_t)DEFAULT_RCBA;
/* Link2: component ID 1 (MCH), link valid */
DMIBAR32(DMILE2D) =
(DMIBAR32(DMILE2D) & 0xff000000) | (1 << 16) | (1 << 0);
- DMIBAR32(DMILE2A) = DEFAULT_MCHBAR;
+ DMIBAR32(DMILE2A) = (uintptr_t)DEFAULT_MCHBAR;
}
void gm45_late_init(const stepping_t stepping)
diff --git a/src/northbridge/intel/gm45/raminit.c b/src/northbridge/intel/gm45/raminit.c
index 60b05bdcb..2c810de81 100644
--- a/src/northbridge/intel/gm45/raminit.c
+++ b/src/northbridge/intel/gm45/raminit.c
@@ -1579,15 +1579,15 @@ static void jedec_init(const timings_t *const timings,
const u32 rankaddr = raminit_get_rank_addr(ch, r);
printk(BIOS_DEBUG, "Performing Jedec initialization at address 0x%08x.\n", rankaddr);
MCHBAR32(DCC_MCHBAR) = (MCHBAR32(DCC_MCHBAR) & ~DCC_SET_EREG_MASK) | DCC_SET_EREGx(2);
- read32(rankaddr | WL);
+ read32((u32 *)(rankaddr | WL));
MCHBAR32(DCC_MCHBAR) = (MCHBAR32(DCC_MCHBAR) & ~DCC_SET_EREG_MASK) | DCC_SET_EREGx(3);
- read32(rankaddr);
+ read32((u32 *)rankaddr);
MCHBAR32(DCC_MCHBAR) = (MCHBAR32(DCC_MCHBAR) & ~DCC_SET_EREG_MASK) | DCC_SET_EREGx(1);
- read32(rankaddr | ODT_120OHMS | ODS_34OHMS);
+ read32((u32 *)(rankaddr | ODT_120OHMS | ODS_34OHMS));
MCHBAR32(DCC_MCHBAR) = (MCHBAR32(DCC_MCHBAR) & ~DCC_CMD_MASK) | DCC_SET_MREG;
- read32(rankaddr | WR | DLL1 | CAS | INTERLEAVED);
+ read32((u32 *)(rankaddr | WR | DLL1 | CAS | INTERLEAVED));
MCHBAR32(DCC_MCHBAR) = (MCHBAR32(DCC_MCHBAR) & ~DCC_CMD_MASK) | DCC_SET_MREG;
- read32(rankaddr | WR | CAS | INTERLEAVED);
+ read32((u32 *)(rankaddr | WR | CAS | INTERLEAVED));
}
}
@@ -1701,7 +1701,7 @@ void raminit(sysinfo_t *const sysinfo, const int s3resume)
/* Wait for some bit, maybe TXT clear. */
if (sysinfo->txt_enabled) {
- while (!(read8(0xfed40000) & (1 << 7))) {}
+ while (!(read8((u8 *)0xfed40000) & (1 << 7))) {}
}
/* Enable SMBUS. */
diff --git a/src/northbridge/intel/gm45/raminit_read_write_training.c b/src/northbridge/intel/gm45/raminit_read_write_training.c
index 5149c2b11..b03cb33c7 100644
--- a/src/northbridge/intel/gm45/raminit_read_write_training.c
+++ b/src/northbridge/intel/gm45/raminit_read_write_training.c
@@ -114,7 +114,7 @@ static int read_training_test(const int channel, const int lane,
for (i = 0; i < addresses->count; ++i) {
unsigned int offset;
for (offset = lane_offset; offset < 320; offset += 8) {
- const u32 read = read32(addresses->addr[i] + offset);
+ const u32 read = read32((u32 *)(addresses->addr[i] + offset));
const u32 good = read_training_schedule[offset >> 3];
if ((read & lane_mask) != (good & lane_mask))
return 0;
@@ -228,7 +228,7 @@ static void perform_read_training(const dimminfo_t *const dimms)
/* Write test pattern. */
unsigned int offset;
for (offset = 0; offset < 320; offset += 4)
- write32(addresses.addr[i] + offset,
+ write32((u32 *)(addresses.addr[i] + offset),
read_training_schedule[offset >> 3]);
}
@@ -436,18 +436,18 @@ static int write_training_test(const address_bunch_t *const addresses,
unsigned int off;
for (off = 0; off < 640; off += 8) {
const u32 pattern = write_training_schedule[off >> 3];
- write32(addr + off, pattern);
- write32(addr + off + 4, pattern);
+ write32((u32 *)(addr + off), pattern);
+ write32((u32 *)(addr + off + 4), pattern);
}
MCHBAR8(0x78) |= 1;
for (off = 0; off < 640; off += 8) {
const u32 good = write_training_schedule[off >> 3];
- const u32 read1 = read32(addr + off);
+ const u32 read1 = read32((u32 *)(addr + off));
if ((read1 & masks[0]) != (good & masks[0]))
goto _bad_timing_out;
- const u32 read2 = read32(addr + off + 4);
+ const u32 read2 = read32((u32 *)(addr + off + 4));
if ((read2 & masks[1]) != (good & masks[1]))
goto _bad_timing_out;
}
diff --git a/src/northbridge/intel/gm45/raminit_receive_enable_calibration.c b/src/northbridge/intel/gm45/raminit_receive_enable_calibration.c
index 5130b599f..62be05e8c 100644
--- a/src/northbridge/intel/gm45/raminit_receive_enable_calibration.c
+++ b/src/northbridge/intel/gm45/raminit_receive_enable_calibration.c
@@ -147,7 +147,7 @@ static int read_dqs_level(const int channel, const int lane)
MCHBAR32(mchbar) |= (1 << 9);
/* Read from this channel. */
- read32(raminit_get_rank_addr(channel, 0));
+ read32((u32 *)raminit_get_rank_addr(channel, 0));
mchbar = 0x14b0 + (channel * 0x0100) + ((7 - lane) * 4);
return MCHBAR32(mchbar) & (1 << 30);