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authorTimothy Pearson <tpearson@raptorengineeringinc.com>2015-04-06 22:01:23 -0500
committerPatrick Georgi <pgeorgi@google.com>2015-05-08 21:28:34 +0200
commite7f70907bab2d511e94482eb606f6e3e629f52f9 (patch)
treea21f3c6c64802396bbc8e8688a2cc05e8810cc2a /src/northbridge/intel/gm45/gma.c
parent59c2c8b07966a06fd742bc79efb960b8a900fbbc (diff)
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northbridge/intel/gm45/gma: Add backlight control register field
This allows the backlight control register to be set via devicetree.cb Change-Id: I32b42dfc1cc609fb6f8995c6158c85be67633770 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/9330 Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/northbridge/intel/gm45/gma.c')
-rw-r--r--src/northbridge/intel/gm45/gma.c8
1 files changed, 6 insertions, 2 deletions
diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c
index 4cf277616..b08422a02 100644
--- a/src/northbridge/intel/gm45/gma.c
+++ b/src/northbridge/intel/gm45/gma.c
@@ -446,12 +446,13 @@ static void gma_func0_init(struct device *dev)
/* Init graphics power management */
gtt_res = find_resource(dev, PCI_BASE_ADDRESS_0);
+ struct northbridge_intel_gm45_config *conf = dev->chip_info;
+
#if !CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT
/* PCI Init, will run VBIOS */
pci_dev_init(dev);
#else
u32 physbase;
- struct northbridge_intel_gm45_config *conf = dev->chip_info;
struct resource *lfb_res;
struct resource *pio_res;
@@ -475,7 +476,10 @@ static void gma_func0_init(struct device *dev)
/* Post VBIOS init */
/* Enable Backlight */
gtt_write(BLC_PWM_CTL2, (1 << 31));
- gtt_write(BLC_PWM_CTL, 0x06100610);
+ if (conf->gfx.backlight == 0)
+ gtt_write(BLC_PWM_CTL, 0x06100610);
+ else
+ gtt_write(BLC_PWM_CTL, conf->gfx.backlight);
}
static void gma_set_subsystem(device_t dev, unsigned vendor, unsigned device)