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authorAlexandru Gagniuc <mr.nuke.me@gmail.com>2015-02-14 02:00:32 -0600
committerAlexandru Gagniuc <mr.nuke.me@gmail.com>2015-02-14 22:54:01 +0100
commit4b10dec1a66122b515b2191f823d7fd379ec655f (patch)
treee80d293bd0d0d346f920d9735278b16fee55b7b3 /src/northbridge/intel/gm45/gma.c
parent24501cae529a51ab9304721be0ec60384ab81ee0 (diff)
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cpu/allwinner/a10/Kconfig: Link ramstage at base of SDRAM
The default linking behavior of ramstage was changed in commit * 8f99378 ARMv7/Exynos: Fix memory location assumptions However, that commit failed to address the issue of maintaining linking behavior on non-Exynos chips. As a result we ended up linking ramstage at address 0, which is outside of SDRAM. Explicitly link ramstage at SDRAM base for A10. This patch does not address the issue on other chips that were broken by commit 8f99378. Change-Id: I90fa41d3eabf110b5ab24c31b78ac6d0474e4083 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/8443 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/northbridge/intel/gm45/gma.c')
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