aboutsummaryrefslogtreecommitdiffstats
path: root/src/include
diff options
context:
space:
mode:
authorAaron Durbin <adurbin@chromium.org>2015-03-06 23:17:33 -0600
committerAaron Durbin <adurbin@chromium.org>2015-04-22 17:55:08 +0200
commitbd74a4b2d25268f7035a4478da31f27baac2aecc (patch)
tree56740c02fe396df8ccf9fc2e7401542deeebf453 /src/include
parentcac50506238507328b8ea0f4abd458869803e6c2 (diff)
downloadcoreboot-bd74a4b2d25268f7035a4478da31f27baac2aecc.tar.gz
coreboot-bd74a4b2d25268f7035a4478da31f27baac2aecc.tar.xz
coreboot-bd74a4b2d25268f7035a4478da31f27baac2aecc.zip
coreboot: common stage cache
Many chipsets were using a stage cache for reference code or when using a relocatable ramstage. Provide a common API for the chipsets to use while reducing code duplication. Change-Id: Ia36efa169fe6bd8a3dbe07bf57a9729c7edbdd46 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/8625 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Diffstat (limited to 'src/include')
-rw-r--r--src/include/cbfs.h3
-rw-r--r--src/include/cbmem.h2
-rw-r--r--src/include/program_loading.h14
-rw-r--r--src/include/ramstage_cache.h53
-rw-r--r--src/include/romstage_handoff.h4
-rw-r--r--src/include/stage_cache.h49
6 files changed, 54 insertions, 71 deletions
diff --git a/src/include/cbfs.h b/src/include/cbfs.h
index 086fa19eb..05ce2f7f3 100644
--- a/src/include/cbfs.h
+++ b/src/include/cbfs.h
@@ -2,7 +2,7 @@
* This file is part of the coreboot project.
*
* Copyright (C) 2008 Jordan Crouse <jordan@cosmicpenguin.net>
- * Copyright (C) 2013 The Chromium OS Authors. All rights reserved.
+ * Copyright (C) 2013-2015 Google, Inc.
*
* This file is dual-licensed. You can choose between:
* - The GNU GPL, version 2, as published by the Free Software Foundation
@@ -90,4 +90,3 @@ void cbfs_set_header_offset(size_t offset);
static inline void cbfs_set_header_offset(size_t offset) {}
#endif
#endif
-
diff --git a/src/include/cbmem.h b/src/include/cbmem.h
index 615510b1f..8c61cb2a1 100644
--- a/src/include/cbmem.h
+++ b/src/include/cbmem.h
@@ -78,6 +78,8 @@
#define CBMEM_ID_SMBIOS 0x534d4254
#define CBMEM_ID_SMM_SAVE_SPACE 0x07e9acee
#define CBMEM_ID_SPINTABLE 0x59175917
+#define CBMEM_ID_STAGEx_META 0x57a9e000
+#define CBMEM_ID_STAGEx_CACHE 0x57a9e100
#define CBMEM_ID_TIMESTAMP 0x54494d45
#define CBMEM_ID_VBOOT_HANDOFF 0x780074f0
#define CBMEM_ID_WIFI_CALIBRATION 0x57494649
diff --git a/src/include/program_loading.h b/src/include/program_loading.h
index 269988777..02e6f5fdb 100644
--- a/src/include/program_loading.h
+++ b/src/include/program_loading.h
@@ -123,18 +123,8 @@ void run_romstage(void);
/* Run ramstage from romstage. */
void run_ramstage(void);
-struct romstage_handoff;
-#if IS_ENABLED(CONFIG_RELOCATABLE_RAMSTAGE)
-/* Cache the loaded ramstage described by prog. */
-void cache_loaded_ramstage(struct romstage_handoff *, struct prog *p);
-/* Load ramstage from cache filling in struct prog. */
-void load_cached_ramstage(struct romstage_handoff *h, struct prog *p);
-#else
-static inline void cache_loaded_ramstage(struct romstage_handoff *h,
- struct prog *p) {}
-static inline void load_cached_ramstage(struct romstage_handoff *h,
- struct prog *p) {}
-#endif
+/* Called when the stage cache couldn't load ramstage on resume. */
+void ramstage_cache_invalid(void);
/***********************
* PAYLOAD LOADING *
diff --git a/src/include/ramstage_cache.h b/src/include/ramstage_cache.h
deleted file mode 100644
index 8d9b09517..000000000
--- a/src/include/ramstage_cache.h
+++ /dev/null
@@ -1,53 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2013 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#ifndef _RAMSTAGE_CACHE_
-#define _RAMSTAGE_CACHE_
-
-#include <stddef.h>
-#include <stdint.h>
-
-/* This structure is saved along with the relocated ramstage program when
- * CONFIG_RELOCATED_RAMSTAGE is employed. For x86, it can used to protect
- * the integrity of the ramstage program on S3 resume by saving a copy of
- * the relocated ramstage in SMM space with the assumption that the SMM region
- * cannot be altered from the OS. The magic value just serves as a quick sanity
- * check. */
-
-#define RAMSTAGE_CACHE_MAGIC 0xf3c3a02a
-
-struct ramstage_cache {
- uint32_t magic;
- uint32_t entry_point;
- uint32_t load_address;
- uint32_t size;
- char program[0];
-} __attribute__((packed));
-
-/* Chipset/Board function for obtaining cache location and size. */
-struct ramstage_cache *ramstage_cache_location(long *size);
-/* Chipset/Board function called when cache is invalid on resume. */
-void ramstage_cache_invalid(struct ramstage_cache *cache);
-
-static inline int ramstage_cache_is_valid(const struct ramstage_cache *c)
-{
- return (c != NULL && c->magic == RAMSTAGE_CACHE_MAGIC);
-}
-
-#endif /* _RAMSTAGE_CACHE_ */
diff --git a/src/include/romstage_handoff.h b/src/include/romstage_handoff.h
index 376b4fd11..09934ca44 100644
--- a/src/include/romstage_handoff.h
+++ b/src/include/romstage_handoff.h
@@ -36,10 +36,6 @@ struct romstage_handoff {
uint8_t s3_resume;
uint8_t reboot_required;
uint8_t reserved[2];
- /* The ramstage_entry_point is cached in the stag loading path. This
- * cached value can only be utilized when the chipset code properly
- * fills in the s3_resume field above. */
- uint32_t ramstage_entry_point;
};
#if defined(__ROMSTAGE__)
diff --git a/src/include/stage_cache.h b/src/include/stage_cache.h
new file mode 100644
index 000000000..bde53307a
--- /dev/null
+++ b/src/include/stage_cache.h
@@ -0,0 +1,49 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifndef _STAGE_CACHE_H_
+#define _STAGE_CACHE_H_
+
+#include <stddef.h>
+#include <stdint.h>
+#include <program_loading.h>
+
+enum {
+ STAGE_RAMSTAGE,
+ STAGE_REFCODE,
+};
+
+/* Create an empty stage cache. */
+void stage_cache_create_empty(void);
+/* Recover existing stage cache. */
+void stage_cache_recover(void);
+/* Cache the loaded stage provided according to the parameters. */
+void stage_cache_add(int stage_id, struct prog *stage);
+/* Load the cached stage at given location returning the stage entry point. */
+void stage_cache_load_stage(int stage_id, struct prog *stage);
+/* Fill in parameters for the external stage cache, if utilized. */
+void stage_cache_external_region(void **base, size_t *size);
+
+/* Metadata associated with each stage. */
+struct stage_cache {
+ uint64_t load_addr;
+ uint64_t entry_addr;
+};
+
+#endif /* _STAGE_CACHE_H_ */