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authorMarc Jones <marc.jones@se-eng.com>2014-09-24 10:53:48 -0600
committerStefan Reinauer <stefan.reinauer@coreboot.org>2015-04-10 19:21:49 +0200
commit9afc5c05f083631424e4e6a86a6c08fcc3e6473b (patch)
tree2ac70a3444b8a96c2332a4f25fd4731467817130 /src/include
parent1376b680c24025234e8bad0e7982dfca4dc1afec (diff)
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baytrail: Switch from ACPI mode to PCI mode for legacy support
Most Baytrail based devices MMIO registers are reported in ACPI space and the device's PCI config space is disabled. The PCI config space is required for many "legacy" OSs that don't have the ACPI driver loading mechanism. Depthcharge signals the legacy boot path via the SMI 0xCC and the coreboot SMI handler can switch the device specific registers to re-enable PCI config space. BUG=chrome-os-partner:30836 BRANCH=None TEST=Build and boot Rambi SeaBIOS. Change-Id: I87248936e2a7e026f38c147bdf0df378e605e370 Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: dbb9205ee22ffce44e965be51ae0bc62d4ca5dd4 Original-Change-Id: Ia5e54f4330eda10a01ce3de5aa4d86779d6e1bf9 Original-Signed-off-by: Marc Jones <marc.jones@se-eng.com> Original-Reviewed-on: https://chromium-review.googlesource.com/219801 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Mike Loptien <mike.loptien@se-eng.com> Original-Tested-by: Mike Loptien <mike.loptien@se-eng.com> Reviewed-on: http://review.coreboot.org/9459 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/include')
-rw-r--r--src/include/cpu/x86/smm.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/src/include/cpu/x86/smm.h b/src/include/cpu/x86/smm.h
index c16a6c50d..adaf74b7a 100644
--- a/src/include/cpu/x86/smm.h
+++ b/src/include/cpu/x86/smm.h
@@ -460,6 +460,7 @@ typedef struct {
#define APM_CNT_MBI_UPDATE 0xeb
#define APM_CNT_GNVS_UPDATE 0xea
#define APM_CNT_FINALIZE 0xcb
+#define APM_CNT_LEGACY 0xcc
#define APM_STS 0xb3
/* SMI handler function prototypes */