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authorRonald G. Minnich <rminnich@google.com>2013-02-20 09:24:29 -0800
committerRonald G. Minnich <rminnich@gmail.com>2013-02-20 20:49:16 +0100
commit601b27596ffdf526adf5b41c1f8366a5fdddc554 (patch)
tree44aa556afd60417cc313be8463cf650b27debfd7 /src/cpu/armltd/cortex-a9
parentc9f35f5300c8c4a171fa7f8d1f35732e88563e7e (diff)
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ARMV7: minor tweaks to inter-stage calling and payload handling.
Payloads, by design, can return. There's lots of mechanism in the payload code to support it, and the chooser payload relies on it. Hence, we should not mark the function call in exit_stage as noreturn. Not all ARM have unified caches, and it's not always easy to tell what to do. So we are very paranoid. Before we call between stages, we should carefully flush the dcache to memory and invalidate the icache. This may be more than is necessary on all architectures but it doesn't really hurt for the most part. So compile cache management code into all stages, and call the flush dcache/invalidate icache from all stages. Change-Id: Ib9cc625c4dfd2d7d4b3c69a74686cc655a9d6484 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/2462 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/cpu/armltd/cortex-a9')
-rw-r--r--src/cpu/armltd/cortex-a9/Makefile.inc1
1 files changed, 1 insertions, 0 deletions
diff --git a/src/cpu/armltd/cortex-a9/Makefile.inc b/src/cpu/armltd/cortex-a9/Makefile.inc
index d1e7edfde..f1a368969 100644
--- a/src/cpu/armltd/cortex-a9/Makefile.inc
+++ b/src/cpu/armltd/cortex-a9/Makefile.inc
@@ -1,2 +1,3 @@
ramstage-y += cache.c
romstage-y += cache.c
+bootblock-y += cache.c