aboutsummaryrefslogtreecommitdiffstats
path: root/src/arch
diff options
context:
space:
mode:
authorJoseph Lo <josephl@nvidia.com>2015-04-07 14:49:22 +0800
committerPatrick Georgi <pgeorgi@google.com>2015-04-22 08:59:28 +0200
commitd1a21d7d7182a40f06f8ec4ff216454fd3c8c1cc (patch)
treeb34a8607e0edb02c72becb2f16f55e6ab9e160e8 /src/arch
parente1741c512c66c468f3c3399aff451ae428cd6824 (diff)
downloadcoreboot-d1a21d7d7182a40f06f8ec4ff216454fd3c8c1cc.tar.gz
coreboot-d1a21d7d7182a40f06f8ec4ff216454fd3c8c1cc.tar.xz
coreboot-d1a21d7d7182a40f06f8ec4ff216454fd3c8c1cc.zip
arm64: add arm64_arch_timer_init function
Add arm64_arch_timer_init function which should be called per CPU for setting up the cntfrq register of arch timer. During the Linux kernel bring up time, it will check the cntfrq register per CPU and should be the same with the boot CPU. BRANCH=none BUG=none TEST=bring up 4 cores in Linux kernel without warning message of cntfrq register value Change-Id: I9cb33a54c2c8f9115bbe545a2338ca8e249b8db6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 253cd3c68bb4513ae2033c12c2f070ee391e5a13 Original-Change-Id: I71068dbdd00a719145410ef6ec466f001ae837ad Original-Signed-off-by: Joseph Lo <josephl@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/264244 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9915 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/arch')
-rw-r--r--src/arch/arm64/cpu_ramstage.c9
-rw-r--r--src/arch/arm64/include/armv8/arch/cpu.h6
2 files changed, 15 insertions, 0 deletions
diff --git a/src/arch/arm64/cpu_ramstage.c b/src/arch/arm64/cpu_ramstage.c
index 369bae3c1..d105b0cfd 100644
--- a/src/arch/arm64/cpu_ramstage.c
+++ b/src/arch/arm64/cpu_ramstage.c
@@ -20,6 +20,7 @@
#include <stdint.h>
#include <stdlib.h>
#include <arch/cache.h>
+#include <arch/cpu.h>
#include <arch/lib_helpers.h>
#include <cpu/cpu.h>
#include <console/console.h>
@@ -27,6 +28,11 @@
#include <timer.h>
#include "cpu-internal.h"
+void __attribute__((weak)) arm64_arch_timer_init(void)
+{
+ /* Default weak implementation does nothing. */
+}
+
static inline void cpu_disable_dev(device_t dev)
{
dev->enabled = 0;
@@ -136,6 +142,9 @@ static void init_this_cpu(void *arg)
* TTA [28] = 0, disable traps for trace register access from EL0/EL1.
*/
raw_write_cpacr_el1(CPACR_TRAP_FP_DISABLE | CPACR_TTA_DISABLE);
+
+ /* Arch Timer init: setup cntfrq per CPU */
+ arm64_arch_timer_init();
}
/* Fill in cpu_info structures according to device tree. */
diff --git a/src/arch/arm64/include/armv8/arch/cpu.h b/src/arch/arm64/include/armv8/arch/cpu.h
index 34220d979..14635e39c 100644
--- a/src/arch/arm64/include/armv8/arch/cpu.h
+++ b/src/arch/arm64/include/armv8/arch/cpu.h
@@ -181,4 +181,10 @@ void arm64_cpu_startup(void);
*/
void arm64_cpu_startup_resume(void);
+/*
+ * The arm64_arch_timer_init() initializes the per CPU's cntfrq register of
+ * ARM arch timer.
+ */
+void arm64_arch_timer_init(void);
+
#endif /* __ARCH_CPU_H__ */