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authorVadim Bendebury <vbendeb@chromium.org>2015-03-02 11:33:13 -0800
committerPatrick Georgi <pgeorgi@google.com>2015-04-21 08:24:39 +0200
commitbe7124ee1d5f42eee86485968374c312ef57d5a1 (patch)
treeda37271a7d44c19762460f11037f10c20fe22973 /src/arch
parent90fe5824b124bcb415e3535722e0653505d66cc4 (diff)
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armv7: preserve bootblock invocation parameter
Some platforms may pass as a parameter the maskrom or vendor startup code information when calling the bootblock. Make sure the bootblock startup code saves this parameter for use by coreboot. As we don't want to touch memory before caches are initialized, save the passed in parameter in r10 for the duration of cache initialization. Added warning comments to help enforcing that cache initialization code does not touch r10. BRANCH=storm BUG=chrome-os-partner:30623 TEST=with the rest of the patches applied see the QCA uber-sbl report in the coreboot console output. Change-Id: Ic6a09e8c3cf13ac4f2d12ee91c7ab41bc9aa95da Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: e41584f769eb042604883275b0d0bdfbf5b0d358 Original-Change-Id: I517a79dc95040326f46f0b80ee4e74bdddde8bf4 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/255144 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Commit-Queue: Vadim Bendebury <vbendeb@gmail.com> Reviewed-on: http://review.coreboot.org/9842 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/arch')
-rw-r--r--src/arch/arm/armv7/bootblock.S23
-rw-r--r--src/arch/arm/armv7/cpu.S4
2 files changed, 25 insertions, 2 deletions
diff --git a/src/arch/arm/armv7/bootblock.S b/src/arch/arm/armv7/bootblock.S
index b468e15c9..57d72d010 100644
--- a/src/arch/arm/armv7/bootblock.S
+++ b/src/arch/arm/armv7/bootblock.S
@@ -32,6 +32,16 @@
#include <arch/asm.h>
.arm
+ /*
+ * Just in case the maskrom or the vendor basic firmware passes on a
+ * parameter when calling the bootblock, store it here for handling by C
+ * code.
+ */
+ .section .bss, "aw" @nobits
+ .global maskrom_param
+maskrom_param:
+ .word 0
+
ENTRY(_start)
/*
* Set the cpu to System mode with IRQ and FIQ disabled. Prefetch/Data
@@ -45,6 +55,10 @@ ENDPROC(_start)
.thumb
ENTRY(_thumb_start)
+
+ /* Preserve the maskrom passed value, if any */
+ mov r10, r0
+
bl arm_init_caches
/*
@@ -71,9 +85,14 @@ init_stack_loop:
cmp r0, r1
bne init_stack_loop
-/* Set stackpointer in internal RAM to call bootblock main() */
call_bootblock:
- ldr sp, =_estack /* Set up stack pointer */
+
+ /* Restore parameter passed in by maskrom/vendor firmware. */
+ ldr r0, =maskrom_param
+ str r10, [r0]
+
+ /* Set stackpointer in internal RAM to call bootblock main() */
+ ldr sp, =_estack
ldr r0,=0x00000000
/*
* The current design of cpu_info places the struct at the top of the
diff --git a/src/arch/arm/armv7/cpu.S b/src/arch/arm/armv7/cpu.S
index b7f245b85..6c00f6258 100644
--- a/src/arch/arm/armv7/cpu.S
+++ b/src/arch/arm/armv7/cpu.S
@@ -43,6 +43,8 @@
* through the magic of double subtraction. It's quite ingenius, really.
* Takes care to only use r0-r3 and ip so it's pefectly ABI-compatible without
* needing to write to memory.
+ *
+ * THIS FUNCTION MUST PRESERVE THE VALUE OF r10
*/
.macro dcache_apply_all crm
@@ -109,6 +111,8 @@
* known state regarding caches/SCTLR. Completely cleans and invalidates
* icache/dcache, disables MMU and dcache (if active), and enables unaligned
* accesses, icache and branch prediction (if inactive). Clobbers r4 and r5.
+ *
+ * THIS FUNCTION MUST PRESERVE THE VALUE OF r10
*/
ENTRY(arm_init_caches)
/* r4: SCTLR, return address: r5 (stay valid for the whole function) */