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authorAaron Durbin <adurbin@chromium.org>2015-03-18 17:02:28 -0500
committerPatrick Georgi <pgeorgi@google.com>2015-04-22 08:42:36 +0200
commita612fc1202322ee9a1017828a9a5cc53d3ffd3cf (patch)
tree164781a1f339ff49ff6ae73965505cc18dc9541f /src/arch
parentb41914952d1f7e2e9f896edd05924deb5b610dff (diff)
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arm64: provide icache_invalidate_all()
In order to not duplicate the instruction cache invalidation sequence provide a common routine to perform the necessary actions. Also, use it in the appropriate places. BUG=None BRANCH=None TEST=Built on ryu. Change-Id: I29ea2371d034c0193949ebb10beb840e7215281a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: d5ab28b5d73c03adcdc0fd4e530b39a7a8989dae Original-Change-Id: I8d5f648c995534294e3222e2dc2091a075dd6beb Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/260949 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9871 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/arch')
-rw-r--r--src/arch/arm64/armv8/cache.c4
-rw-r--r--src/arch/arm64/armv8/secmon_loader.c3
-rw-r--r--src/arch/arm64/include/armv8/arch/cache.h11
3 files changed, 15 insertions, 3 deletions
diff --git a/src/arch/arm64/armv8/cache.c b/src/arch/arm64/armv8/cache.c
index c1dba9259..d568f261e 100644
--- a/src/arch/arm64/armv8/cache.c
+++ b/src/arch/arm64/armv8/cache.c
@@ -144,7 +144,5 @@ void dcache_mmu_enable(void)
void cache_sync_instructions(void)
{
flush_dcache_all(); /* includes trailing DSB (in assembly) */
- iciallu(); /* includes BPIALLU (architecturally) */
- dsb();
- isb();
+ icache_invalidate_all(); /* includdes leading DSB and trailing ISB. */
}
diff --git a/src/arch/arm64/armv8/secmon_loader.c b/src/arch/arm64/armv8/secmon_loader.c
index 7a6e3ee73..d3eda185d 100644
--- a/src/arch/arm64/armv8/secmon_loader.c
+++ b/src/arch/arm64/armv8/secmon_loader.c
@@ -22,6 +22,7 @@
* and parameter location for the rmodule.
*/
+#include <arch/cache.h>
#include <arch/lib_helpers.h>
#include <arch/secmon.h>
#include <arch/spintable.h>
@@ -106,6 +107,8 @@ static void secmon_start(void *arg)
scr |= SCR_NS;
raw_write_scr_el3(scr);
+ /* Invalidate instruction cache. Necessary for non-BSP. */
+ icache_invalidate_all();
entry(p);
}
diff --git a/src/arch/arm64/include/armv8/arch/cache.h b/src/arch/arm64/include/armv8/arch/cache.h
index 6ee610125..27fe8e059 100644
--- a/src/arch/arm64/include/armv8/arch/cache.h
+++ b/src/arch/arm64/include/armv8/arch/cache.h
@@ -86,4 +86,15 @@ void cache_sync_instructions(void);
/* tlb invalidate all */
void tlb_invalidate_all(void);
+/* Invalidate all of the instruction cache for PE to PoU. */
+static inline void icache_invalidate_all(void)
+{
+ __asm__ __volatile__(
+ "dsb sy\n\t"
+ "ic iallu\n\t"
+ "dsb sy\n\t"
+ "isb\n\t"
+ : : : "memory");
+}
+
#endif /* ARM_ARM64_CACHE_H */