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authorYen Lin <yelin@nvidia.com>2015-03-24 11:15:10 -0700
committerPatrick Georgi <pgeorgi@google.com>2015-04-22 08:48:10 +0200
commit900059a2236424ca70cb29cc4af3ac5cf47712fd (patch)
tree1d53444b2823ba2d19e1a68ad905725e6ed46464 /src/arch
parentf7c5c610a2563971461bbc066117d185022df0f5 (diff)
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arch/arm64: allow floating-point registers access
BRANCH=None BUG=None TEST=build coreboot, make sure there are fmov instructions generated by the compiler, and boot to kernel Change-Id: Ia99c710be77d5baec7a743a726257ef3ec782635 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: f770a436a0692c8e57a8c80860a180330b71e82c Original-Change-Id: Iab4ba979b483d19fe92b8a75d9b881a57985eed7 Original-Signed-off-by: Yen Lin <yelin@nvidia.com> Original-Signed-off-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/262242 Original-Tested-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9884 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/arch')
-rw-r--r--src/arch/arm64/cpu_ramstage.c19
-rw-r--r--src/arch/arm64/include/armv8/arch/lib_helpers.h22
2 files changed, 41 insertions, 0 deletions
diff --git a/src/arch/arm64/cpu_ramstage.c b/src/arch/arm64/cpu_ramstage.c
index 466ca0124..369bae3c1 100644
--- a/src/arch/arm64/cpu_ramstage.c
+++ b/src/arch/arm64/cpu_ramstage.c
@@ -117,6 +117,25 @@ static void init_this_cpu(void *arg)
printk(BIOS_DEBUG, "%s init\n", dev_path(dev));
dev->ops->init(dev);
}
+
+ /*
+ * Disable coprocessor traps to EL3:
+ * TCPAC [20] = 0, disable traps for EL2 accesses to CPTR_EL2 or HCPTR
+ * and EL2/EL1 access to CPACR_EL1.
+ * TTA [20] = 0, disable traps for trace register access from any EL.
+ * TFP [10] = 0, disable traps for floating-point instructions from any
+ * EL.
+ */
+ raw_write_cptr_el3(CPTR_EL3_TCPAC_DISABLE | CPTR_EL3_TTA_DISABLE |
+ CPTR_EL3_TFP_DISABLE);
+
+ /*
+ * Allow FPU accesses:
+ * FPEN [21:20] = 3, disable traps for floating-point instructions from
+ * EL0/EL1.
+ * TTA [28] = 0, disable traps for trace register access from EL0/EL1.
+ */
+ raw_write_cpacr_el1(CPACR_TRAP_FP_DISABLE | CPACR_TTA_DISABLE);
}
/* Fill in cpu_info structures according to device tree. */
diff --git a/src/arch/arm64/include/armv8/arch/lib_helpers.h b/src/arch/arm64/include/armv8/arch/lib_helpers.h
index ba41f4544..1e04d48cf 100644
--- a/src/arch/arm64/include/armv8/arch/lib_helpers.h
+++ b/src/arch/arm64/include/armv8/arch/lib_helpers.h
@@ -126,6 +126,28 @@
#define SCTLR_LITTLE_END (0 << SCTLR_ENDIAN_SHIFT)
#define SCTLR_BIG_END (1 << SCTLR_ENDIAN_SHIFT)
+#define CPTR_EL3_TCPAC_SHIFT (31)
+#define CPTR_EL3_TTA_SHIFT (20)
+#define CPTR_EL3_TFP_SHIFT (10)
+#define CPTR_EL3_TCPAC_DISABLE (0 << CPTR_EL3_TCPAC_SHIFT)
+#define CPTR_EL3_TCPAC_ENABLE (1 << CPTR_EL3_TCPAC_SHIFT)
+#define CPTR_EL3_TTA_DISABLE (0 << CPTR_EL3_TTA_SHIFT)
+#define CPTR_EL3_TTA_ENABLE (1 << CPTR_EL3_TTA_SHIFT)
+#define CPTR_EL3_TFP_DISABLE (0 << CPTR_EL3_TFP_SHIFT)
+#define CPTR_EL3_TFP_ENABLE (1 << CPTR_EL3_TFP_SHIFT)
+
+#define CPACR_TTA_SHIFT (28)
+#define CPACR_TTA_ENABLE (1 << CPACR_TTA_SHIFT)
+#define CPACR_TTA_DISABLE (0 << CPACR_TTA_SHIFT)
+#define CPACR_FPEN_SHIFT (20)
+/*
+ * ARMv8-A spec: Values 0b00 and 0b10 both seem to enable traps from el0 and el1
+ * for fp reg access.
+ */
+#define CPACR_TRAP_FP_EL0_EL1 (0 << CPACR_FPEN_SHIFT)
+#define CPACR_TRAP_FP_EL0 (1 << CPACR_FPEN_SHIFT)
+#define CPACR_TRAP_FP_DISABLE (3 << CPACR_FPEN_SHIFT)
+
#ifdef __ASSEMBLY__
/* Macro to switch to label based on current el */