path: root/src/arch/x86/init
diff options
authorJulius Werner <jwerner@chromium.org>2014-08-20 15:29:56 -0700
committerPatrick Georgi <pgeorgi@google.com>2015-04-06 22:05:01 +0200
commitec5e5e0db2ac923a4f80d24ffa7582c3b821d971 (patch)
treea9d8c7d6a0fab0cc2c41c9de4ec39f355289a72b /src/arch/x86/init
parent06ef04604570d402687245521731053c66888b15 (diff)
New mechanism to define SRAM/memory map with automatic bounds checking
This patch creates a new mechanism to define the static memory layout (primarily in SRAM) for a given board, superseding the brittle mass of Kconfigs that we were using before. The core part is a memlayout.ld file in the mainboard directory (although boards are expected to just include the SoC default in most cases), which is the primary linker script for all stages (though not rmodules for now). It uses preprocessor macros from <memlayout.h> to form a different valid linker script for all stages while looking like a declarative, boilerplate-free map of memory addresses to the programmer. Linker asserts will automatically guarantee that the defined regions cannot overlap. Stages are defined with a maximum size that will be enforced by the linker. The file serves to both define and document the memory layout, so that the documentation cannot go missing or out of date. The mechanism is implemented for all boards in the ARM, ARM64 and MIPS architectures, and should be extended onto all systems using SRAM in the future. The CAR/XIP environment on x86 has very different requirements and the layout is generally not as static, so it will stay like it is and be unaffected by this patch (save for aligning some symbol names for consistency and sharing the new common ramstage linker script include). BUG=None TEST=Booted normally and in recovery mode, checked suspend/resume and the CBMEM console on Falco, Blaze (both normal and vboot2), Pinky and Pit. Compiled Ryu, Storm and Urara, manually compared the disassemblies with ToT and looked for red flags. Change-Id: Ifd2276417f2036cbe9c056f17e42f051bcd20e81 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: f1e2028e7ebceeb2d71ff366150a37564595e614 Original-Change-Id: I005506add4e8fcdb74db6d5e6cb2d4cb1bd3cda5 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/213370 Reviewed-on: http://review.coreboot.org/9283 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Tauner <stefan.tauner@gmx.at> Reviewed-by: Aaron Durbin <adurbin@google.com>
Diffstat (limited to 'src/arch/x86/init')
1 files changed, 4 insertions, 4 deletions
diff --git a/src/arch/x86/init/romstage.ld b/src/arch/x86/init/romstage.ld
index 40ed3544a..2ae96aca4 100644
--- a/src/arch/x86/init/romstage.ld
+++ b/src/arch/x86/init/romstage.ld
@@ -60,12 +60,12 @@ SECTIONS
_car_data_end = .;
/* The preram cbmem console area comes last to take advantage
- * of a zero-sized array to hold the memconsole contents that
- * grows to a bound of CONFIG_CONSOLE_PRERAM_BUFFER_SIZE.
+ * of a zero-sized array to hold the memconsole contents.
* However, collisions within the cache-as-ram region cannot be
* statically checked because the cache-as-ram region usage is
* cpu/chipset dependent. */
- preram_cbmem_console = .;
+ _preram_cbmem_console = .;
+ _epreram_cbmem_console = . + 0xc00;
/* Global variables are not allowed in romstage
@@ -83,5 +83,5 @@ SECTIONS
- _bogus = ASSERT((SIZEOF(.car.data) + CONFIG_CONSOLE_PRERAM_BUFFER_SIZE <= CONFIG_DCACHE_RAM_SIZE), "Cache as RAM area is too full");
+ _bogus = ASSERT((CONFIG_DCACHE_RAM_SIZE == 0) || (SIZEOF(.car.data) + 0xc00 <= CONFIG_DCACHE_RAM_SIZE), "Cache as RAM area is too full");