aboutsummaryrefslogtreecommitdiffstats
path: root/src/arch/x86/init
diff options
context:
space:
mode:
authorStefan Reinauer <stepan@coreboot.org>2010-12-11 20:33:41 +0000
committerStefan Reinauer <stepan@openbios.org>2010-12-11 20:33:41 +0000
commit8677a23d5b053d550f70246de9c7dc8fd4e2fbf9 (patch)
treed9a7c6042de85d623739e2679ba90c66aad2797f /src/arch/x86/init
parent198cb96387c457affa01696405ffaa4531e8e361 (diff)
downloadcoreboot-8677a23d5b053d550f70246de9c7dc8fd4e2fbf9.tar.gz
coreboot-8677a23d5b053d550f70246de9c7dc8fd4e2fbf9.tar.xz
coreboot-8677a23d5b053d550f70246de9c7dc8fd4e2fbf9.zip
After this has been brought up many times before, rename src/arch/i386 to
src/arch/x86. Signed-off-by: Stefan Reinauer <stepan@coreboot.org> Acked-by: Patrick Georgi <patrick@georgi-clan.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6161 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/arch/x86/init')
-rw-r--r--src/arch/x86/init/Makefile.inc1
-rw-r--r--src/arch/x86/init/bootblock_normal.c26
-rw-r--r--src/arch/x86/init/bootblock_simple.c15
-rw-r--r--src/arch/x86/init/crt0_romcc_epilogue.inc26
-rw-r--r--src/arch/x86/init/entry.S149
-rw-r--r--src/arch/x86/init/ldscript.ld40
-rw-r--r--src/arch/x86/init/ldscript_apc.lb31
-rw-r--r--src/arch/x86/init/ldscript_failover.lb53
-rw-r--r--src/arch/x86/init/ldscript_fallback_cbfs.lb53
-rw-r--r--src/arch/x86/init/prologue.inc29
10 files changed, 423 insertions, 0 deletions
diff --git a/src/arch/x86/init/Makefile.inc b/src/arch/x86/init/Makefile.inc
new file mode 100644
index 000000000..263c58e89
--- /dev/null
+++ b/src/arch/x86/init/Makefile.inc
@@ -0,0 +1 @@
+# If you add something to this file, enable it in src/arch/x86/Makefile.inc first.
diff --git a/src/arch/x86/init/bootblock_normal.c b/src/arch/x86/init/bootblock_normal.c
new file mode 100644
index 000000000..08651c32b
--- /dev/null
+++ b/src/arch/x86/init/bootblock_normal.c
@@ -0,0 +1,26 @@
+#include <bootblock_common.h>
+#include <pc80/mc146818rtc.h>
+
+static void main(unsigned long bist)
+{
+ if (boot_cpu()) {
+ bootblock_northbridge_init();
+ bootblock_southbridge_init();
+ }
+
+ unsigned long entry;
+ if (do_normal_boot())
+ entry = findstage("normal/romstage");
+ else
+ entry = findstage("fallback/romstage");
+
+ if (entry) call(entry, bist);
+
+ /* run fallback if normal can't be found */
+ entry = findstage("fallback/romstage");
+ if (entry) call(entry, bist);
+
+ /* duh. we're stuck */
+ asm volatile ("1:\n\thlt\n\tjmp 1b\n\t");
+}
+
diff --git a/src/arch/x86/init/bootblock_simple.c b/src/arch/x86/init/bootblock_simple.c
new file mode 100644
index 000000000..e8994ee09
--- /dev/null
+++ b/src/arch/x86/init/bootblock_simple.c
@@ -0,0 +1,15 @@
+#include <bootblock_common.h>
+
+static void main(unsigned long bist)
+{
+ if (boot_cpu()) {
+ bootblock_northbridge_init();
+ bootblock_southbridge_init();
+ }
+ const char* target1 = "fallback/romstage";
+ unsigned long entry;
+ entry = findstage(target1);
+ if (entry) call(entry, bist);
+ asm volatile ("1:\n\thlt\n\tjmp 1b\n\t");
+}
+
diff --git a/src/arch/x86/init/crt0_romcc_epilogue.inc b/src/arch/x86/init/crt0_romcc_epilogue.inc
new file mode 100644
index 000000000..3bd1b3699
--- /dev/null
+++ b/src/arch/x86/init/crt0_romcc_epilogue.inc
@@ -0,0 +1,26 @@
+/*
+ * Copyright 2002 Eric Biederman
+ *
+ * This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of the License.
+ */
+
+ /* clear boot_complete flag */
+ xorl %ebp, %ebp
+__main:
+ post_code(0x11)
+ cld /* clear direction flag */
+
+ movl %ebp, %esi
+
+ movl $ROMSTAGE_STACK, %esp
+ movl %esp, %ebp
+ pushl %esi
+ call copy_and_run
+
+.Lhlt:
+ post_code(0xee)
+ hlt
+ jmp .Lhlt
+
diff --git a/src/arch/x86/init/entry.S b/src/arch/x86/init/entry.S
new file mode 100644
index 000000000..af2929640
--- /dev/null
+++ b/src/arch/x86/init/entry.S
@@ -0,0 +1,149 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 1999 Ronald G. Minnich
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+#include <arch/rom_segs.h>
+ .code16
+ .globl _stage0
+_stage0:
+ cli
+
+ /* Save the BIST result. */
+ movl %eax, %ebp;
+
+ /* thanks to kmliu@sis.com.tw for this TLB fix */
+ /* IMMEDIATELY invalidate the translation lookaside buffer (TLB) before
+ * executing any further code. Even though paging is disabled we
+ * could still get false address translations due to the TLB if we
+ * didn't invalidate it.
+ */
+ xorl %eax, %eax
+ movl %eax, %cr3 /* Invalidate TLB. */
+
+ /* Switch to protected mode. */
+
+ /* NOTE: With GNU assembler version 2.15.94.0.2.2 (i386-redhat-linux)
+ * using BFD version 2.15.94.0.2.2 20041220 this works fine without all
+ * the ld hackery and other things. So leave it as is with this comment.
+ */
+
+ data32 lgdt %cs:gdtptr
+
+ movl %cr0, %eax
+ andl $0x7FFAFFD1, %eax /* PG, AM, WP, NE, TS, EM, MP = 0 */
+ orl $0x60000001, %eax /* CD, NW, PE = 1 */
+ movl %eax, %cr0
+
+ /* Restore BIST result. */
+ movl %ebp, %eax
+
+ // port80_post(0x23)
+ /* Now we are in protected mode. Jump to a 32 bit code segment. */
+ data32 ljmp $ROM_CODE_SEG, $protected_stage0
+
+ /* I am leaving this weird jump in here in the event that future gas
+ * bugs force it to be used.
+ */
+ /* .byte 0x66 */
+ .code32
+ /* ljmp $ROM_CODE_SEG, $protected_stage0 */
+
+ /* .code16 */
+ .align 4
+ .globl gdt16
+gdt16 = . - _stage0
+gdt16x:
+ .word gdt16xend - gdt16x -1 /* Compute the table limit. */
+ .long gdt16x
+ .word 0
+
+ /* selgdt 0x08, flat code segment */
+ .word 0xffff, 0x0000
+ .byte 0x00, 0x9b, 0xcf, 0x00
+
+ /* selgdt 0x10, flat data segment */
+ .word 0xffff, 0x0000
+ .byte 0x00, 0x93, 0xcf, 0x00
+gdt16xend:
+
+ /* From now on we are 32 bit. */
+ .code32
+
+ /* We have two gdts where we could have one. That is ok.
+ *
+ * Let's not worry about this -- optimizing gdt is pointless since
+ * we're only in it for a little bit.
+ *
+ * Btw. note the trick below: The GDT points to ITSELF, and the first
+ * good descriptor is at offset 8. So you word-align the table, and
+ * then because you chose 8, you get a nice 64-bit aligned GDT entry,
+ * which is good as this is the size of the entry.
+ * Just in case you ever wonder why people do this.
+ */
+ .align 4
+ .globl gdtptr
+ .globl gdt_limit
+gdt_limit = gdt_end - gdt - 1 /* Compute the table limit. */
+
+gdt:
+gdtptr:
+ .word gdt_end - gdt -1 /* Compute the table limit. */
+ .long gdt /* We know the offset. */
+ .word 0
+
+ /* selgdt 0x08, flat code segment */
+ .word 0xffff, 0x0000
+ .byte 0x00, 0x9b, 0xcf, 0x00
+
+ /* selgdt 0x10, flat data segment */
+ .word 0xffff, 0x0000
+ .byte 0x00, 0x93, 0xcf, 0x00
+
+gdt_end:
+
+/* Reset vector. */
+
+/*
+ * RVECTOR: Size of reset vector, default is 0x10.
+ * RESRVED: Size of vpd code, default is 0xf0.
+ * BOOTBLK: Size of bootblock code, default is 0x1f00 (8k-256b).
+ */
+
+SEGMENT_SIZE = 0x10000
+RVECTOR = 0x00010
+
+/* Due to YET ANOTHER BUG in GNU bintools, you can NOT have a code16 here.
+ * I think we should leave it this way forever, as the bugs come and
+ * go -- and come again.
+ *
+ * .code16
+ * .section ".rom.text"
+ */
+.section ".reset", "ax"
+ .globl _resetjump
+_resetjump:
+ /* GNU bintools bugs again. This jumps to stage0 - 2. Sigh. */
+ /* jmp _stage0 */
+ .byte 0xe9
+ .int _stage0 - ( . + 2 )
+
+ /* Note: The above jump is hand coded to work around bugs in binutils.
+ * 5 bytes are used for a 3 byte instruction. This works because x86
+ * is little endian and allows us to use supported 32 bit relocations
+ * instead of the weird 16 bit relocations that binutils does not
+ * handle consistenly between versions because they are used so rarely.
+ */
diff --git a/src/arch/x86/init/ldscript.ld b/src/arch/x86/init/ldscript.ld
new file mode 100644
index 000000000..149f04863
--- /dev/null
+++ b/src/arch/x86/init/ldscript.ld
@@ -0,0 +1,40 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Ronald G. Minnich <rminnich@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+TARGET(binary)
+SECTIONS
+{
+ /DISCARD/ : {
+ *(.comment)
+ *(.note.*)
+ *(.note)
+ }
+}
+
+SECTIONS {
+ _ROMTOP = 0xfffffff0;
+ . = _ROMTOP;
+ .resetvector . : {
+ *(.reset)
+ . = 15 ;
+ BYTE(0x00);
+ }
+}
+
diff --git a/src/arch/x86/init/ldscript_apc.lb b/src/arch/x86/init/ldscript_apc.lb
new file mode 100644
index 000000000..789a168e0
--- /dev/null
+++ b/src/arch/x86/init/ldscript_apc.lb
@@ -0,0 +1,31 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2006 Advanced Micro Devices, Inc.
+ * Copyright (C) 2008-2010 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+INCLUDE "ldoptions"
+SECTIONS
+{
+ .apcrom . : {
+ _apcrom = .;
+ *(.text)
+ *(.rodata)
+ *(.rodata.*)
+ _eapcrom = .;
+ }
+}
diff --git a/src/arch/x86/init/ldscript_failover.lb b/src/arch/x86/init/ldscript_failover.lb
new file mode 100644
index 000000000..7e48dc1a2
--- /dev/null
+++ b/src/arch/x86/init/ldscript_failover.lb
@@ -0,0 +1,53 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2006 Advanced Micro Devices, Inc.
+ * Copyright (C) 2008-2010 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* We use ELF as output format. So that we can debug the code in some form. */
+OUTPUT_FORMAT("elf32-i386", "elf32-i386", "elf32-i386")
+OUTPUT_ARCH(i386)
+
+MEMORY {
+ rom : ORIGIN = 0xffff0000, LENGTH = 64K
+}
+
+TARGET(binary)
+SECTIONS
+{
+ /* This section might be better named .setup */
+ .rom ROMLOC : {
+ _rom = .;
+ *(.rom.text);
+ *(.rom.data);
+ *(.rom.data.*);
+ *(.rodata.*);
+ _erom = .;
+ } >rom = 0xff
+
+ ROMLOC = 0xffffff00 - (_erom - _rom) + 1;
+
+ /DISCARD/ : {
+ *(.comment)
+ *(.note)
+ *(.comment.*)
+ *(.note.*)
+ *(.iplt)
+ *(.rel.*)
+ *(.igot.*)
+ }
+}
diff --git a/src/arch/x86/init/ldscript_fallback_cbfs.lb b/src/arch/x86/init/ldscript_fallback_cbfs.lb
new file mode 100644
index 000000000..480fd32d5
--- /dev/null
+++ b/src/arch/x86/init/ldscript_fallback_cbfs.lb
@@ -0,0 +1,53 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2006 Advanced Micro Devices, Inc.
+ * Copyright (C) 2008-2010 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* We use ELF as output format. So that we can debug the code in some form. */
+OUTPUT_FORMAT("elf32-i386", "elf32-i386", "elf32-i386")
+OUTPUT_ARCH(i386)
+
+TARGET(binary)
+SECTIONS
+{
+ . = CONFIG_ROMBASE;
+
+ /* cut _start into last 64k*/
+ _x = .;
+ . = (_x < (CONFIG_ROMBASE - 0x10000 + CONFIG_ROM_IMAGE_SIZE)) ? (CONFIG_ROMBASE - 0x10000 + CONFIG_ROM_IMAGE_SIZE) : _x;
+
+ /* This section might be better named .setup */
+ .rom . : {
+ _rom = .;
+ *(.rom.text);
+ *(.rom.data);
+ *(.rodata);
+ *(.rodata.*);
+ *(.rom.data.*);
+ . = ALIGN(16);
+ _erom = .;
+ }
+
+ /DISCARD/ : {
+ *(.comment)
+ *(.note)
+ *(.comment.*)
+ *(.note.*)
+ }
+ _bogus = ASSERT((SIZEOF(.bss) + SIZEOF(.data)) == 0, "Do not use global variables in romstage");
+}
diff --git a/src/arch/x86/init/prologue.inc b/src/arch/x86/init/prologue.inc
new file mode 100644
index 000000000..8947f20de
--- /dev/null
+++ b/src/arch/x86/init/prologue.inc
@@ -0,0 +1,29 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2002 Eric Biederman
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <cpu/x86/post_code.h>
+#include <cpu/x86/stack.h>
+
+.section ".rom.data", "a", @progbits
+.section ".rom.text", "ax", @progbits
+
+/* This is the entry code. The code in the .reset section jumps here. */
+
+ post_code(0x01)
+