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authorKyösti Mälkki <kyosti.malkki@gmail.com>2012-02-14 10:39:17 +0200
committerPatrick Georgi <patrick@georgi-clan.de>2012-03-31 11:57:47 +0200
commit7dfe32c5408916b6cb23f1ec48e473e1c728d300 (patch)
tree0bc84bfc3dc17928607826398614d942051d3e7f /src/arch/x86/init
parentf9d1a42d98b121088b0c242b4d9f5d0eb78d38de (diff)
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Add support for RAM-less multi-processor init
For a hyper-threading processor, enabling cache requires that both the BSP and AP CPU clear CR0.CD (Cache Disable) bit. For a Cache-As-Ram implementation, partial multi-processor initialisation precedes raminit and AP CPUs' 16bit entry must be run from ROM. The AP CPU can only start execute real-mode code at a 4kB aligned address below 1MB. The protected mode entry code for AP is identical with the BSP code, which is already located at the top of bootblock. This patch takes the simplest approach and aligns the bootblock 16 bit entry at highest possible 4kB boundary below 1MB. The symbol ap_sipi_vector is tested to match CONFIG_AP_SIPI_VECTOR used by the CAR code in romstage. Adress is not expected to ever change, but if it does, link will fail. Change-Id: I82e4edbf208c9ba863f51a64e50cd92871c528ef Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/454 Tested-by: build bot (Jenkins) Reviewed-by: Idwer Vollering <vidwer@gmail.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/arch/x86/init')
-rw-r--r--src/arch/x86/init/ldscript_failover.lb13
1 files changed, 9 insertions, 4 deletions
diff --git a/src/arch/x86/init/ldscript_failover.lb b/src/arch/x86/init/ldscript_failover.lb
index 83e5eb343..61c3d2a35 100644
--- a/src/arch/x86/init/ldscript_failover.lb
+++ b/src/arch/x86/init/ldscript_failover.lb
@@ -29,17 +29,18 @@ MEMORY {
TARGET(binary)
SECTIONS
{
- /* Align .rom to next 4 byte boundary so no pad byte appears
- * between _rom and _start.
+ /* Symbol ap_sipi_vector must be aligned to 4kB to start AP CPUs
+ * with Startup IPI message without RAM.
*/
.bogus ROMLOC_MIN : {
- . = ALIGN(4);
+ . = ALIGN(4096);
ROMLOC = .;
} >rom = 0xff
/* This section might be better named .setup */
.rom ROMLOC : {
_rom = .;
+ ap_sipi_vector = .;
*(.rom.text);
*(.rom.data);
*(.rom.data.*);
@@ -51,7 +52,11 @@ SECTIONS
* may cause the total size of a section to change when the start
* address gets applied.
*/
- ROMLOC_MIN = 0xffffff00 - (_erom - _rom + 16);
+ ROMLOC_MIN = 0xffffff00 - (_erom - _rom + 16) - 4096;
+
+ /* Post-check proper SIPI vector. */
+ _bogus = ASSERT(((ap_sipi_vector & 0x0fff) == 0x0), "Bad SIPI vector alignment");
+ _bogus = ASSERT((ap_sipi_vector == CONFIG_AP_SIPI_VECTOR), "Address mismatch on AP_SIPI_VECTOR");
/DISCARD/ : {
*(.comment)