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authorJulius Werner <jwerner@chromium.org>2014-08-20 15:29:56 -0700
committerPatrick Georgi <pgeorgi@google.com>2015-04-06 22:05:01 +0200
commitec5e5e0db2ac923a4f80d24ffa7582c3b821d971 (patch)
treea9d8c7d6a0fab0cc2c41c9de4ec39f355289a72b /src/arch/mips/ramstage.ld
parent06ef04604570d402687245521731053c66888b15 (diff)
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New mechanism to define SRAM/memory map with automatic bounds checking
This patch creates a new mechanism to define the static memory layout (primarily in SRAM) for a given board, superseding the brittle mass of Kconfigs that we were using before. The core part is a memlayout.ld file in the mainboard directory (although boards are expected to just include the SoC default in most cases), which is the primary linker script for all stages (though not rmodules for now). It uses preprocessor macros from <memlayout.h> to form a different valid linker script for all stages while looking like a declarative, boilerplate-free map of memory addresses to the programmer. Linker asserts will automatically guarantee that the defined regions cannot overlap. Stages are defined with a maximum size that will be enforced by the linker. The file serves to both define and document the memory layout, so that the documentation cannot go missing or out of date. The mechanism is implemented for all boards in the ARM, ARM64 and MIPS architectures, and should be extended onto all systems using SRAM in the future. The CAR/XIP environment on x86 has very different requirements and the layout is generally not as static, so it will stay like it is and be unaffected by this patch (save for aligning some symbol names for consistency and sharing the new common ramstage linker script include). BUG=None TEST=Booted normally and in recovery mode, checked suspend/resume and the CBMEM console on Falco, Blaze (both normal and vboot2), Pinky and Pit. Compiled Ryu, Storm and Urara, manually compared the disassemblies with ToT and looked for red flags. Change-Id: Ifd2276417f2036cbe9c056f17e42f051bcd20e81 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: f1e2028e7ebceeb2d71ff366150a37564595e614 Original-Change-Id: I005506add4e8fcdb74db6d5e6cb2d4cb1bd3cda5 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/213370 Reviewed-on: http://review.coreboot.org/9283 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Tauner <stefan.tauner@gmx.at> Reviewed-by: Aaron Durbin <adurbin@google.com>
Diffstat (limited to 'src/arch/mips/ramstage.ld')
-rw-r--r--src/arch/mips/ramstage.ld121
1 files changed, 0 insertions, 121 deletions
diff --git a/src/arch/mips/ramstage.ld b/src/arch/mips/ramstage.ld
deleted file mode 100644
index 405244446..000000000
--- a/src/arch/mips/ramstage.ld
+++ /dev/null
@@ -1,121 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Imagination Technologies
- *
- * Based on src/arch/arm/ramstage.ld:
- * Written by Johan Rydberg, based on work by Daniel Kahlin.
- * Rewritten by Eric Biederman
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-OUTPUT_ARCH(mips)
-
-ENTRY(stage_entry)
-
-PHDRS
-{
- to_load PT_LOAD;
-}
-
-SECTIONS
-{
- . = CONFIG_SYS_SDRAM_BASE;
-
- .text : {
- _text = .;
- _start = .;
- *(.text.stage_entry.mips);
- *(.text);
- *(.text.*);
- . = ALIGN(16);
- _etext = .;
- } : to_load
-
- .ctors : {
- . = ALIGN(0x100);
- __CTOR_LIST__ = .;
- *(.ctors);
- LONG(0);
- __CTOR_END__ = .;
- }
-
- .rodata : {
- _rodata = .;
- . = ALIGN(4);
- console_drivers = .;
- KEEP(*(.rodata.console_drivers));
- econsole_drivers = . ;
- . = ALIGN(4);
- pci_drivers = . ;
- KEEP(*(.rodata.pci_driver));
- epci_drivers = . ;
- cpu_drivers = . ;
- KEEP(*(.rodata.cpu_driver));
- ecpu_drivers = . ;
- _bs_init_begin = .;
- KEEP(*(.bs_init));
- _bs_init_end = .;
- *(.rodata)
- *(.rodata.*)
- . = ALIGN(4);
- _erodata = .;
- }
-
- .data : {
- _data = .;
- *(.data)
- _edata = .;
- }
-
- /* bss will be cleared by cbfs_load_stage */
- _bss = .;
- .bss . : {
- *(.bss)
- *(.sbss)
- *(COMMON)
- }
- _ebss = .;
- _end = .;
-
- /*
- * coreboot from the perspective of the loader really "ends"
- * here. Only symbols are placed after this.
- */
-
- _heap = .;
- _eheap = . + CONFIG_HEAP_SIZE;
-
- _stack = CONFIG_STACK_BOTTOM;
- _estack = CONFIG_STACK_TOP;
-
- /*
- * The ram segment. This includes all memory used by the memory
- * resident copy of coreboot, except the tables that are produced on
- * the fly, but including stack and heap.
- */
- _ram_seg = _text;
- _eram_seg = _eheap;
-
- /* Discard the sections we don't need/want */
-
- /DISCARD/ : {
- *(.comment)
- *(.note)
- *(.note.*)
- }
-}