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authorAndrew Bresticker <abrestic@chromium.org>2015-02-05 13:31:41 -0800
committerPatrick Georgi <pgeorgi@google.com>2015-04-21 08:12:07 +0200
commit3537e956e1ee2d189876fb47a09b65e96ed3c8f4 (patch)
tree484c9a8b41be11273089bba3cfff6bb285803ac8 /src/arch/mips/Makefile.inc
parentdf4081e72cda341236350647f96b419e03b9edce (diff)
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mips: Allow memory to be identity mapped in the TLB
Introduce identity_map() function. It takes a memory range and identity maps it entirely in the TLB table, if possible. As a result the virtual and physical address ranges are the same. The function attempts to use as large of a page size as possible for each region in order to conserve TLB entries. BUG=chrome-os-partner:36258 BRANCH=none TEST=Build and boot on Pistachio with the rest of the patches applied. Change-Id: I4d781b04699e069a71c49a0c6ca15c7a6b42a468 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 234d32edfd201019b7a723316a79c932c62ce87e Original-Change-Id: If3e2392b19555cb6dbae8b5559c1b1e53a313637 Original-Signed-off-by: Andrew Bresticker <abrestic@chromium.org> Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/246693 Reviewed-on: http://review.coreboot.org/9815 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/arch/mips/Makefile.inc')
-rw-r--r--src/arch/mips/Makefile.inc3
1 files changed, 3 insertions, 0 deletions
diff --git a/src/arch/mips/Makefile.inc b/src/arch/mips/Makefile.inc
index 1016f1f79..358e71ddf 100644
--- a/src/arch/mips/Makefile.inc
+++ b/src/arch/mips/Makefile.inc
@@ -37,6 +37,7 @@ bootblock-y += boot.c
bootblock-y += bootblock.S
bootblock-y += bootblock_simple.c
bootblock-y += cache.c
+bootblock-y += mmu.c
bootblock-y += stages.c
bootblock-y += ../../lib/memcpy.c
bootblock-y += ../../lib/memmove.c
@@ -63,6 +64,7 @@ ifeq ($(CONFIG_ARCH_ROMSTAGE_MIPS),y)
romstage-y += boot.c
romstage-$(CONFIG_EARLY_CONSOLE) += early_console.c
romstage-y += cache.c
+romstage-y += mmu.c
romstage-y += stages.c
romstage-y += ../../lib/memcpy.c
romstage-y += ../../lib/memmove.c
@@ -83,6 +85,7 @@ ifeq ($(CONFIG_ARCH_RAMSTAGE_MIPS),y)
ramstage-y += ashldi3.c
ramstage-y += boot.c
ramstage-y += cache.c
+ramstage-y += mmu.c
ramstage-y += stages.c
ramstage-y += tables.c
ramstage-y += ../../lib/memcpy.c