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authorJoseph Lo <josephl@nvidia.com>2015-04-17 15:31:59 +0800
committerPatrick Georgi <pgeorgi@google.com>2015-04-27 07:45:34 +0200
commitd8a5017ee0d47e860148d139bc5329083ac06515 (patch)
treed7e60204a154442b8fc882d03765a6659209ea20 /src/arch/arm64/include/arch
parentc38d3e8131b0f6ed7e576d1a66ac9513b1810f27 (diff)
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arm64: save/restore cptr_el3 and cpacr_el1 registers
CPTR_EL3 and CPACR_EL1 are the registers for controlling the trap level and access right of the FPU/SIMD instructions. Need to save/restore them in every power cycle to keep the settings consistent. BRANCH=none BUG=none TEST=boot on smaug/foster, verify the cpu_on/off is ok as well Change-Id: I96fc0e0d2620e72b6ae2ffe4d073c9328047dc01 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 73e8cc8f25922e7bc218d24fbf4f7c67e15e3057 Original-Change-Id: I51eed07b1bb8f6eb2715622ec5d5c3f80c3c8bdd Original-Signed-off-by: Joseph Lo <josephl@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/266073 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Benson Leung <bleung@chromium.org> Reviewed-on: http://review.coreboot.org/9981 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Diffstat (limited to 'src/arch/arm64/include/arch')
-rw-r--r--src/arch/arm64/include/arch/startup.h4
1 files changed, 3 insertions, 1 deletions
diff --git a/src/arch/arm64/include/arch/startup.h b/src/arch/arm64/include/arch/startup.h
index 671c13e4c..6e55190e8 100644
--- a/src/arch/arm64/include/arch/startup.h
+++ b/src/arch/arm64/include/arch/startup.h
@@ -30,8 +30,10 @@
#define SCR_INDEX 3
#define VBAR_INDEX 4
#define CNTFRQ_INDEX 5
+#define CPTR_INDEX 6
+#define CPACR_INDEX 7
/* IMPORTANT!!! If any new element is added please update NUM_ELEMENTS */
-#define NUM_ELEMENTS 6
+#define NUM_ELEMENTS 8
#ifndef __ASSEMBLY__