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authorDaisuke Nojiri <dnojiri@chromium.org>2014-09-04 09:55:34 -0700
committerAaron Durbin <adurbin@google.com>2015-03-24 14:48:04 +0100
commitefddcfbb52cd328ad2eb86d88cd306ac30294109 (patch)
tree0cf0e5aff39826797f48a3f040be9d50ce3cdb73 /src/arch/arm/verstage.ld
parent1b05d887d702fcf5ac704d2ee5257122a180694c (diff)
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vboot2: separate verstage from bootblock
With CONFIG_RETURN_FROM_VERSTAGE false, the verstage loads the romstage over the bootblock, then exits to the romstage. this is necessary for some SOC (e.g. tegra124) which runs the bootblock on a different architecture. With CONFIG_RETURN_FROM_VERSTAGE true, the verstage returns to the bootblock. Then, the bootblock loads the romstage over the verstage and exits to the romstage. this is probably necessary for some SOC (e.g. rockchip) which does not have SRAM big enough to fit the verstage and the romstage at the same time. BUG=none TEST=Built Blaze with USE=+/-vboot2. Ran faft on Blaze. BRANCH=none Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Change-Id: I673945c5e21afc800d523fbb25d49fdc83693544 Original-Reviewed-on: https://chromium-review.googlesource.com/212365 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Note: This purposefully is probably broken in vendorcode/google/chromeos as I'm just trying to set a base for dropping more patches in. The vboot paths will have to change from how they are currently constructed. (cherry picked from commit 4fa17395113d86445660091413ecb005485f8014) Signed-off-by: Aaron Durbin <adurbin@chromium.org> Change-Id: I9117434ce99695f9b7021a06196d864f180df5c9 Reviewed-on: http://review.coreboot.org/8881 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/arch/arm/verstage.ld')
-rw-r--r--src/arch/arm/verstage.ld67
1 files changed, 67 insertions, 0 deletions
diff --git a/src/arch/arm/verstage.ld b/src/arch/arm/verstage.ld
new file mode 100644
index 000000000..f0e88e590
--- /dev/null
+++ b/src/arch/arm/verstage.ld
@@ -0,0 +1,67 @@
+/*
+ * Memory map:
+ *
+ * CONFIG_VERSTAGE_BASE : text segment
+ * : rodata segment
+ * : data segment
+ * : bss segment
+ */
+
+/* We use ELF as output format. So that we can debug the code in some form. */
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+INCLUDE ldoptions
+
+PHDRS
+{
+ to_load PT_LOAD;
+}
+
+ENTRY(stage_entry)
+
+SECTIONS
+{
+ . = CONFIG_VERSTAGE_BASE;
+
+ .romtext . : {
+ _start = .;
+ *(.text.stage_entry.arm);
+ *(.text.startup);
+ *(.text);
+ *(.text.*);
+ } : to_load
+
+ .romdata . : {
+ *(.rodata);
+ *(.rodata.*);
+ *(.data);
+ *(.data.*);
+ . = ALIGN(8);
+ }
+
+ /* bss does not contain data, it is just a space that should be zero
+ * initialized on startup. (typically uninitialized global variables)
+ */
+ .bss . : {
+ . = ALIGN(8);
+ _bss = .;
+ *(.bss)
+ *(.bss.*)
+ *(.sbss)
+ *(.sbss.*)
+ _ebss = .;
+ }
+
+ _end = .;
+
+ preram_cbmem_console = CONFIG_CONSOLE_PRERAM_BUFFER_BASE;
+
+ /* Discard the sections we don't need/want */
+ /DISCARD/ : {
+ *(.comment)
+ *(.note)
+ *(.comment.*)
+ *(.note.*)
+ *(.eh_frame);
+ }
+}