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authorJulius Werner <jwerner@chromium.org>2014-10-16 10:23:36 -0700
committerPatrick Georgi <pgeorgi@google.com>2015-04-08 09:28:37 +0200
commitb2b7132fa3bfcdc8fcdb482e528d8f0be6c22556 (patch)
tree7ac16905826e16d74d8f04bcb4db02fce54f827f /payloads
parent0de8820f5f94b307f0fe22e5e01c94e573f5c5ee (diff)
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arm: Dump additional fault registers in abort handlers
Paging code is tricky and figuring out what is wrong with it can be a pain. This patch tries to ease the burden by giving a little more information for prefetch and data aborts, dumping the Instruction Fault Address Register (IFAR), Instruction Fault Status Register (IFSR) and Auxiliary Instruction Fault Status Register (AIFSR) or the respective Data registers. These contain additional information about the cause of the abort (internal/external, write or read, fault subtype, etc.) and the faulting address. BUG=None TEST=I have read through enough imprecise asynchronous external abort reports with this patch that I learned the bit pattern by heart. Change-Id: If1850c4a6df29b1195714ed0bdf025e51220e8ab Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: bf3b4924121825a5ceef7e5c14b7b307d01f8e9c Original-Change-Id: I56a0557d4257f40b5b30c559c84eaf9b9f729099 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/223784 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9345 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'payloads')
-rw-r--r--payloads/libpayload/arch/arm/exception.c12
-rw-r--r--payloads/libpayload/include/arm/arch/cache.h48
2 files changed, 60 insertions, 0 deletions
diff --git a/payloads/libpayload/arch/arm/exception.c b/payloads/libpayload/arch/arm/exception.c
index d10093729..6f1796018 100644
--- a/payloads/libpayload/arch/arm/exception.c
+++ b/payloads/libpayload/arch/arm/exception.c
@@ -90,6 +90,18 @@ void exception_dispatch(u32 idx)
printf("%s Exception\n", names[idx]);
print_regs();
+ switch (idx) {
+ case EXC_PABORT:
+ printf("IFAR = %#.8x\n", read_ifar());
+ printf("IFSR = %#.8x\n", read_ifsr());
+ printf("AIFSR = %#.8x\n", read_aifsr());
+ break;
+ case EXC_DABORT:
+ printf("DFAR = %#.8x\n", read_dfar());
+ printf("DFSR = %#.8x\n", read_dfsr());
+ printf("ADFSR = %#.8x\n", read_adfsr());
+ break;
+ };
dump_stack(exception_state.regs[13], 512);
halt();
}
diff --git a/payloads/libpayload/include/arm/arch/cache.h b/payloads/libpayload/include/arm/arch/cache.h
index 67f6fd449..b258185b9 100644
--- a/payloads/libpayload/include/arm/arch/cache.h
+++ b/payloads/libpayload/include/arm/arch/cache.h
@@ -268,6 +268,54 @@ static inline void write_sctlr(uint32_t val)
isb();
}
+/* read data fault address register (DFAR) */
+static inline uint32_t read_dfar(void)
+{
+ uint32_t val;
+ asm volatile ("mrc p15, 0, %0, c6, c0, 0" : "=r" (val));
+ return val;
+}
+
+/* read data fault status register (DFSR) */
+static inline uint32_t read_dfsr(void)
+{
+ uint32_t val;
+ asm volatile ("mrc p15, 0, %0, c5, c0, 0" : "=r" (val));
+ return val;
+}
+
+/* read instruction fault address register (IFAR) */
+static inline uint32_t read_ifar(void)
+{
+ uint32_t val;
+ asm volatile ("mrc p15, 0, %0, c6, c0, 2" : "=r" (val));
+ return val;
+}
+
+/* read instruction fault status register (IFSR) */
+static inline uint32_t read_ifsr(void)
+{
+ uint32_t val;
+ asm volatile ("mrc p15, 0, %0, c5, c0, 1" : "=r" (val));
+ return val;
+}
+
+/* read auxiliary data fault status register (ADFSR) */
+static inline uint32_t read_adfsr(void)
+{
+ uint32_t val;
+ asm volatile ("mrc p15, 0, %0, c5, c1, 0" : "=r" (val));
+ return val;
+}
+
+/* read auxiliary instruction fault status register (AIFSR) */
+static inline uint32_t read_aifsr(void)
+{
+ uint32_t val;
+ asm volatile ("mrc p15, 0, %0, c5, c1, 1" : "=r" (val));
+ return val;
+}
+
/*
* Cache maintenance API
*/