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authorVadim Bendebury <vbendeb@chromium.org>2015-01-09 16:54:19 -0800
committerPatrick Georgi <pgeorgi@google.com>2015-04-17 09:53:54 +0200
commit6cc5e52ec66585682d251f32f901c4db7b51b4d4 (patch)
treeea93c12fdf5dfb10b5c56ebaa7e92cf8c8f69d07 /payloads
parent9dccf1c40bc2543ad12f6a5af9daea8d0ef0ddfa (diff)
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libpayload: read register width from coreboot table
Some SOCs (like pistachio, for instance) provide an 8250 compatible UART, which has the same register layout, but mapped to a bus of a different width. Instead of adding a new driver for these controllers, it is better to have coreboot report UART register width to libpayload, and have it adjust the offsets accordingly when accessing the UART. BRANCH=none BUG=chrome-os-partner:31438 TEST=with the rest of the patches integrated depthcharge console messages show up when running on the FPGA board Change-Id: I05891a9471a5369d3bfafe90cd0c9b0a7e5a667e Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 2c30845f269ec6ae1d53ddc5cda0b4320008fa42 Original-Change-Id: Ia0a37cd5f24a1ee4d0334f8a7e3da5df0069cec4 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/240027 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9739 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'payloads')
-rw-r--r--payloads/libpayload/drivers/serial/8250.c4
-rw-r--r--payloads/libpayload/include/coreboot_tables.h1
2 files changed, 5 insertions, 0 deletions
diff --git a/payloads/libpayload/drivers/serial/8250.c b/payloads/libpayload/drivers/serial/8250.c
index 0651f5201..bca0057bb 100644
--- a/payloads/libpayload/drivers/serial/8250.c
+++ b/payloads/libpayload/drivers/serial/8250.c
@@ -39,6 +39,8 @@ static int serial_is_mem_mapped = 0;
static uint8_t serial_read_reg(int offset)
{
+ offset *= lib_sysinfo.serial->regwidth;
+
#ifdef CONFIG_LP_IO_ADDRESS_SPACE
if (!serial_is_mem_mapped)
return inb(IOBASE + offset);
@@ -49,6 +51,8 @@ static uint8_t serial_read_reg(int offset)
static void serial_write_reg(uint8_t val, int offset)
{
+ offset *= lib_sysinfo.serial->regwidth;
+
#ifdef CONFIG_LP_IO_ADDRESS_SPACE
if (!serial_is_mem_mapped)
outb(val, IOBASE + offset);
diff --git a/payloads/libpayload/include/coreboot_tables.h b/payloads/libpayload/include/coreboot_tables.h
index 1a189e5e4..c46fbf922 100644
--- a/payloads/libpayload/include/coreboot_tables.h
+++ b/payloads/libpayload/include/coreboot_tables.h
@@ -120,6 +120,7 @@ struct cb_serial {
u32 type;
u32 baseaddr;
u32 baud;
+ u32 regwidth;
};
#define CB_TAG_CONSOLE 0x00010