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authorDan Ehrenberg <dehrenberg@chromium.org>2015-01-08 10:29:19 -0800
committerPatrick Georgi <pgeorgi@google.com>2015-04-17 09:21:12 +0200
commit6addd4026876d48e7205dced69174cd4dfef09bb (patch)
tree371639bbf452168e50eadac1d076beddb99aae3e /payloads
parenta5aac76ac6be23448c164b0bc8047facb7238cdf (diff)
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libpayload: Take flash parameters from coreboot
A payload may want to run erase operations on SPI NOR flash without re-probing the device to get its properties. This patch passes up three properties of flash to achieve that: - The size of the flash device - The sector size, i.e., the granularity of erase - The command used for erase The patch sends the parameters through coreboot and then libpayload. The patch also includes a minor refactoring of the flash erase code. Parameters are sent up for just one flash device. If multiple SPI flash devices are probed, the second one will "win" and its parameters will be sent up to the payload. TEST=Observed parameters to be passed up to depthcharge through libpayload and be used to correctly initialize flash and do an erase. TEST=Winbond and Gigadevices spi flash drivers compile with the changes; others don't, for seemingly unrelated reasons. BRANCH=none BUG=chromium:446377 Change-Id: I92b7ff0ce66af8d096ec09a4c900829ef6c867e0 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 988c8c68bbfcdfa69d497ea5f806567bc80f8126 Original-Change-Id: Ie2b3a7f5b6e016d212f4f9bac3fabd80daf2ce72 Original-Signed-off-by: Dan Ehrenberg <dehrenberg@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/239570 Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: http://review.coreboot.org/9727 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'payloads')
-rw-r--r--payloads/libpayload/include/coreboot_tables.h9
-rw-r--r--payloads/libpayload/include/sysinfo.h5
-rw-r--r--payloads/libpayload/libc/coreboot.c12
3 files changed, 26 insertions, 0 deletions
diff --git a/payloads/libpayload/include/coreboot_tables.h b/payloads/libpayload/include/coreboot_tables.h
index a3a0a05a3..1a189e5e4 100644
--- a/payloads/libpayload/include/coreboot_tables.h
+++ b/payloads/libpayload/include/coreboot_tables.h
@@ -246,6 +246,15 @@ struct cb_ram_code {
uint32_t ram_code;
};
+#define CB_TAG_SPI_FLASH 0x0029
+struct cb_spi_flash {
+ uint32_t tag;
+ uint32_t size;
+ uint32_t flash_size;
+ uint32_t sector_size;
+ uint32_t erase_cmd;
+};
+
#define CB_TAG_CMOS_OPTION_TABLE 0x00c8
struct cb_cmos_option_table {
u32 tag;
diff --git a/payloads/libpayload/include/sysinfo.h b/payloads/libpayload/include/sysinfo.h
index aa594c98d..ec8a31c6b 100644
--- a/payloads/libpayload/include/sysinfo.h
+++ b/payloads/libpayload/include/sysinfo.h
@@ -118,6 +118,11 @@ struct sysinfo_t {
void *wifi_calibration;
uint64_t ramoops_buffer;
uint32_t ramoops_buffer_size;
+ struct spi_flash {
+ uint32_t size;
+ uint32_t sector_size;
+ uint32_t erase_cmd;
+ } spi_flash;
};
extern struct sysinfo_t lib_sysinfo;
diff --git a/payloads/libpayload/libc/coreboot.c b/payloads/libpayload/libc/coreboot.c
index 1f1cf320a..5999e8685 100644
--- a/payloads/libpayload/libc/coreboot.c
+++ b/payloads/libpayload/libc/coreboot.c
@@ -203,6 +203,15 @@ static void cb_parse_ramoops(void *ptr, struct sysinfo_t *info)
info->ramoops_buffer_size = ramoops->range_size;
}
+static void cb_parse_spi_flash(void *ptr, struct sysinfo_t *info)
+{
+ struct cb_spi_flash *flash = (struct cb_spi_flash *)ptr;
+
+ info->spi_flash.size = flash->flash_size;
+ info->spi_flash.sector_size = flash->sector_size;
+ info->spi_flash.erase_cmd = flash->erase_cmd;
+}
+
int cb_parse_header(void *addr, int len, struct sysinfo_t *info)
{
struct cb_header *header;
@@ -346,6 +355,9 @@ int cb_parse_header(void *addr, int len, struct sysinfo_t *info)
case CB_TAG_RAM_OOPS:
cb_parse_ramoops(ptr, info);
break;
+ case CB_TAG_SPI_FLASH:
+ cb_parse_spi_flash(ptr, info);
+ break;
default:
cb_parse_arch_specific(rec, info);
break;