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authorAndrew Bresticker <abrestic@chromium.org>2015-02-05 13:51:50 -0800
committerPatrick Georgi <pgeorgi@google.com>2015-04-21 08:13:52 +0200
commit44c51058909ccba2461aca78aa9de131b47b49da (patch)
treeb84c8ba60088490ba79ad5b1297c5db82d41a52a /payloads
parentca0e89b61e06b316c4182091799c5aa333015ebe (diff)
downloadcoreboot-44c51058909ccba2461aca78aa9de131b47b49da.tar.gz
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libpayload: mips: Do not set C0_EBase_WG
The WG (write gate) bit in C0_EBase allows the upper two bits of the exception base address to be set to something other than 2'b10, thus allowing it to be relocated out of the traditional KSEG{0,1} range. Since we're not using the segmentation features introduced by EVA to relocate the unmapped segments, the exception vectors should remain in KSEG0. Don't set the WG bit so that the upper two bits of the exception base (2'b00, because of the identity mapping) are ignored and we execute the exception vectors out of KSEG0. BUG=chrome-os-partner:36258 BRANCH=none TEST=Build and boot on Pistachio. Change-Id: Ie8b4eb6e41a328e7055736c9e3f6ff5ec83b9e13 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: d5b002f5ae71c7729e467d4fe3fd8db187e15dea Original-Change-Id: Id8b930db1e7a68f52dd61be4dfa9edaee2bebf7d Original-Signed-off-by: Andrew Bresticker <abrestic@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/246697 Original-Reviewed-by: Ionela Voinescu <ionela.voinescu@imgtec.com> Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org> Original-Commit-Queue: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: http://review.coreboot.org/9822 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'payloads')
-rw-r--r--payloads/libpayload/arch/mips/exception_asm.S4
1 files changed, 0 insertions, 4 deletions
diff --git a/payloads/libpayload/arch/mips/exception_asm.S b/payloads/libpayload/arch/mips/exception_asm.S
index 5906d39f0..85386ac55 100644
--- a/payloads/libpayload/arch/mips/exception_asm.S
+++ b/payloads/libpayload/arch/mips/exception_asm.S
@@ -20,7 +20,6 @@
#define STATUS_REGISTER $12,0
#define BOOT_EXC_VECTOR_MASK (1 << 22)
#define EBASE_REGISTER $15,1
-#define WRITE_GATE_MASK (1 << 11)
#define EXCEPTION_BASE_MASK (0xFFFFF000)
/* Don't reorder instructions */
@@ -192,9 +191,6 @@ exception_init_asm:
and $t0, $t0, $t2
/* Filling base address */
or $t0, $t0, $t1
- /* Setting WG bit */
- li $t2, WRITE_GATE_MASK
- or $t0, $t0, $t2
mtc0 $t0, EBASE_REGISTER
/* Clear boot exception vector bit for EBASE value to take effect */