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authorDamien Zammit <damien@zamaudio.com>2015-05-03 18:43:04 +1000
committerPatrick Georgi <pgeorgi@google.com>2015-05-08 21:29:04 +0200
commitf88b93214b68581e0c46d0108f3eec9f2fc21b2b (patch)
tree34588d9f87bf68a4acf63d1aac79b24f5e8b2cf7
parente7f70907bab2d511e94482eb606f6e3e629f52f9 (diff)
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southbridge/i82801gx: Add x_EN defines for LPC_EN
A few hardcoded values could be fixed after this commit Change-Id: I3ae67f4f6136361d67d4fdae2a5a29b7b1a75478 Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: http://review.coreboot.org/10065 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
-rw-r--r--src/southbridge/intel/i82801gx/i82801gx.h10
1 files changed, 10 insertions, 0 deletions
diff --git a/src/southbridge/intel/i82801gx/i82801gx.h b/src/southbridge/intel/i82801gx/i82801gx.h
index 815768bbc..512137b0b 100644
--- a/src/southbridge/intel/i82801gx/i82801gx.h
+++ b/src/southbridge/intel/i82801gx/i82801gx.h
@@ -108,6 +108,16 @@ int southbridge_detect_s3_resume(void);
#define LPC_IO_DEC 0x80 /* IO Decode Ranges Register */
#define LPC_EN 0x82 /* LPC IF Enables Register */
+#define CNF2_LPC_EN (1 << 13) /* 0x4e/0x4f */
+#define CNF1_LPC_EN (1 << 12) /* 0x2e/0x2f */
+#define MC_LPC_EN (1 << 11) /* 0x62/0x66 */
+#define KBC_LPC_EN (1 << 10) /* 0x60/0x64 */
+#define GAMEH_LPC_EN (1 << 9) /* 0x208/0x20f */
+#define GAMEL_LPC_EN (1 << 8) /* 0x200/0x207 */
+#define FDD_LPC_EN (1 << 3) /* LPC_IO_DEC[12] */
+#define LPT_LPC_EN (1 << 2) /* LPC_IO_DEC[9:8] */
+#define COMB_LPC_EN (1 << 1) /* LPC_IO_DEC[6:4] */
+#define COMA_LPC_EN (1 << 0) /* LPC_IO_DEC[2:0] */
/* PCI Configuration Space (D31:F1): IDE */
#define INTR_LN 0x3c