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authorhuang lin <hl@rock-chips.com>2015-01-23 16:41:20 +0800
committerStefan Reinauer <stefan.reinauer@coreboot.org>2015-04-15 22:13:40 +0200
commitc14e42623bede2480284cf500362d545f85f8f69 (patch)
treecd146330cfb5596578c1e85d77b06d001dec1dd4
parent1cd2e76f2a7b6e95af8d4f40cd3ee7f5180b8466 (diff)
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rk3288: support edp HPD function
we use the delay 200ms to meet the edp power timing request before, it waste time, so we use the HPD function to detect the edp panel now. In previous version, the hardware may not support the edp HPD function, so in the code it will spend 200ms to detect hpd single, if it don't get the hpd single, it will contiue the edp initialization process, to compatible all of the hardware version. BUG=chrome-os-partner:35623 TEST=Boot from Mighty, and display normal BRANCH=None Change-Id: I82c6a80e37fa42eef3521e6ebbf190d7e80fcece Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Original-Commit-Id: 7a5343eb9af12cae9a15284217762a91ae24bac6 Original-Change-Id: I21c0ef6ce4643e90a192d8b86659264895b5fda9 Original-Signed-off-by: huang lin <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/242792 Original-Reviewed-by: Daniel Kurtz <djkurtz@chromium.org> Reviewed-on: http://review.coreboot.org/9659 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
-rw-r--r--src/mainboard/google/veyron_jerry/devicetree.cb1
-rw-r--r--src/mainboard/google/veyron_jerry/mainboard.c4
-rw-r--r--src/mainboard/google/veyron_mighty/devicetree.cb1
-rw-r--r--src/mainboard/google/veyron_mighty/mainboard.c4
-rw-r--r--src/mainboard/google/veyron_pinky/devicetree.cb1
-rw-r--r--src/mainboard/google/veyron_pinky/mainboard.c4
-rw-r--r--src/mainboard/google/veyron_speedy/devicetree.cb1
-rw-r--r--src/mainboard/google/veyron_speedy/mainboard.c4
-rw-r--r--src/soc/rockchip/rk3288/chip.h1
-rw-r--r--src/soc/rockchip/rk3288/display.c1
-rw-r--r--src/soc/rockchip/rk3288/edp.c45
-rw-r--r--src/soc/rockchip/rk3288/include/soc/grf.h6
12 files changed, 66 insertions, 7 deletions
diff --git a/src/mainboard/google/veyron_jerry/devicetree.cb b/src/mainboard/google/veyron_jerry/devicetree.cb
index 4a2533dcd..59a18267a 100644
--- a/src/mainboard/google/veyron_jerry/devicetree.cb
+++ b/src/mainboard/google/veyron_jerry/devicetree.cb
@@ -22,5 +22,4 @@ chip soc/rockchip/rk3288
device cpu_cluster 0 on end
register "vop_id" = "1"
register "framebuffer_bits_per_pixel" = "16"
- register "lcd_power_on_udelay" = "200000"
end
diff --git a/src/mainboard/google/veyron_jerry/mainboard.c b/src/mainboard/google/veyron_jerry/mainboard.c
index 9300b3684..937b1ad1e 100644
--- a/src/mainboard/google/veyron_jerry/mainboard.c
+++ b/src/mainboard/google/veyron_jerry/mainboard.c
@@ -102,6 +102,10 @@ static void configure_vop(void)
rk808_configure_ldo(7, 2500); /* VCC10_LCD_PWREN_H */
gpio_output(GPIO(7, B, 6), 1); /* LCD_EN */
rk808_configure_switch(1, 1); /* VCC33_LCD */
+
+ /* enable edp HPD */
+ gpio_input_pulldown(GPIO(7, B, 3));
+ writel(IOMUX_EDP_HOTPLUG, &rk3288_grf->iomux_edp_hotplug);
break;
}
}
diff --git a/src/mainboard/google/veyron_mighty/devicetree.cb b/src/mainboard/google/veyron_mighty/devicetree.cb
index 4a2533dcd..59a18267a 100644
--- a/src/mainboard/google/veyron_mighty/devicetree.cb
+++ b/src/mainboard/google/veyron_mighty/devicetree.cb
@@ -22,5 +22,4 @@ chip soc/rockchip/rk3288
device cpu_cluster 0 on end
register "vop_id" = "1"
register "framebuffer_bits_per_pixel" = "16"
- register "lcd_power_on_udelay" = "200000"
end
diff --git a/src/mainboard/google/veyron_mighty/mainboard.c b/src/mainboard/google/veyron_mighty/mainboard.c
index 72141f0f2..e0057c68f 100644
--- a/src/mainboard/google/veyron_mighty/mainboard.c
+++ b/src/mainboard/google/veyron_mighty/mainboard.c
@@ -102,6 +102,10 @@ static void configure_vop(void)
rk808_configure_ldo(7, 2500); /* VCC10_LCD_PWREN_H */
gpio_output(GPIO(7, B, 6), 1); /* LCD_EN */
rk808_configure_switch(1, 1); /* VCC33_LCD */
+
+ /* enable edp HPD */
+ gpio_input_pulldown(GPIO(7, B, 3));
+ writel(IOMUX_EDP_HOTPLUG, &rk3288_grf->iomux_edp_hotplug);
break;
}
}
diff --git a/src/mainboard/google/veyron_pinky/devicetree.cb b/src/mainboard/google/veyron_pinky/devicetree.cb
index 4a2533dcd..59a18267a 100644
--- a/src/mainboard/google/veyron_pinky/devicetree.cb
+++ b/src/mainboard/google/veyron_pinky/devicetree.cb
@@ -22,5 +22,4 @@ chip soc/rockchip/rk3288
device cpu_cluster 0 on end
register "vop_id" = "1"
register "framebuffer_bits_per_pixel" = "16"
- register "lcd_power_on_udelay" = "200000"
end
diff --git a/src/mainboard/google/veyron_pinky/mainboard.c b/src/mainboard/google/veyron_pinky/mainboard.c
index fcd02f513..8e7b20f18 100644
--- a/src/mainboard/google/veyron_pinky/mainboard.c
+++ b/src/mainboard/google/veyron_pinky/mainboard.c
@@ -146,6 +146,10 @@ static void configure_vop(void)
rk808_configure_ldo(7, 2500); /* VCC10_LCD_PWREN_H */
rk808_configure_switch(1, 1); /* VCC33_LCD */
gpio_output(GPIO(7, B, 6), 1); /* LCD_EN */
+
+ /* enable edp HPD */
+ gpio_input_pulldown(GPIO(7, B, 3));
+ writel(IOMUX_EDP_HOTPLUG, &rk3288_grf->iomux_edp_hotplug);
break;
}
}
diff --git a/src/mainboard/google/veyron_speedy/devicetree.cb b/src/mainboard/google/veyron_speedy/devicetree.cb
index 4a2533dcd..59a18267a 100644
--- a/src/mainboard/google/veyron_speedy/devicetree.cb
+++ b/src/mainboard/google/veyron_speedy/devicetree.cb
@@ -22,5 +22,4 @@ chip soc/rockchip/rk3288
device cpu_cluster 0 on end
register "vop_id" = "1"
register "framebuffer_bits_per_pixel" = "16"
- register "lcd_power_on_udelay" = "200000"
end
diff --git a/src/mainboard/google/veyron_speedy/mainboard.c b/src/mainboard/google/veyron_speedy/mainboard.c
index 72141f0f2..e0057c68f 100644
--- a/src/mainboard/google/veyron_speedy/mainboard.c
+++ b/src/mainboard/google/veyron_speedy/mainboard.c
@@ -102,6 +102,10 @@ static void configure_vop(void)
rk808_configure_ldo(7, 2500); /* VCC10_LCD_PWREN_H */
gpio_output(GPIO(7, B, 6), 1); /* LCD_EN */
rk808_configure_switch(1, 1); /* VCC33_LCD */
+
+ /* enable edp HPD */
+ gpio_input_pulldown(GPIO(7, B, 3));
+ writel(IOMUX_EDP_HOTPLUG, &rk3288_grf->iomux_edp_hotplug);
break;
}
}
diff --git a/src/soc/rockchip/rk3288/chip.h b/src/soc/rockchip/rk3288/chip.h
index b401ab4b4..9c65c4daa 100644
--- a/src/soc/rockchip/rk3288/chip.h
+++ b/src/soc/rockchip/rk3288/chip.h
@@ -26,7 +26,6 @@ struct soc_rockchip_rk3288_config {
u32 vop_id;
gpio_t lcd_bl_pwm_gpio;
gpio_t lcd_bl_en_gpio;
- u32 lcd_power_on_udelay;
u32 bl_power_on_udelay;
u32 bl_pwm_to_enable_udelay;
u32 framebuffer_bits_per_pixel;
diff --git a/src/soc/rockchip/rk3288/display.c b/src/soc/rockchip/rk3288/display.c
index 68b4b8f4c..06f0e64cf 100644
--- a/src/soc/rockchip/rk3288/display.c
+++ b/src/soc/rockchip/rk3288/display.c
@@ -56,7 +56,6 @@ void rk_display_init(device_t dev, u32 lcdbase,
rkclk_configure_vop_aclk(conf->vop_id, 192 * MHz);
rk_edp_init(conf->vop_id);
- udelay(conf->lcd_power_on_udelay);
if (rk_edp_get_edid(&edid)) {
printk(BIOS_WARNING, "can not get edid\n");
diff --git a/src/soc/rockchip/rk3288/edp.c b/src/soc/rockchip/rk3288/edp.c
index 7b69ce8d2..3f2719519 100644
--- a/src/soc/rockchip/rk3288/edp.c
+++ b/src/soc/rockchip/rk3288/edp.c
@@ -938,6 +938,49 @@ static int rk_edp_config_video(struct rk_edp *edp)
return rk_edp_is_video_stream_on(edp);
}
+static void rockchip_edp_force_hpd(struct rk_edp *edp)
+{
+ u32 val;
+
+ val = readl(&edp->regs->sys_ctl_3);
+ val |= (F_HPD | HPD_CTRL);
+ writel(val, &edp->regs->sys_ctl_3);
+}
+
+static int rockchip_edp_get_plug_in_status(struct rk_edp *edp)
+{
+ u32 val;
+
+ val = readl(&edp->regs->sys_ctl_3);
+ if (val & HPD_STATUS)
+ return 1;
+
+ return 0;
+}
+
+/*
+ * support edp HPD function
+ * some hardware version do not support edp hdp,
+ * we use 200ms to try to get the hpd single now,
+ * if we can not get edp hpd single, it will delay 200ms,
+ * also meet the edp power timing request, to compatible
+ * all of the hardware version
+ */
+static void rockchip_edp_wait_hpd(struct rk_edp *edp)
+{
+ struct stopwatch hpd;
+
+ stopwatch_init_msecs_expire(&hpd, 200);
+ do {
+ if (rockchip_edp_get_plug_in_status(edp))
+ return;
+ udelay(100);
+ } while (!stopwatch_expired(&hpd));
+
+ printk(BIOS_DEBUG, "do not get hpd single, force hpd\n");
+ rockchip_edp_force_hpd(edp);
+}
+
int rk_edp_get_edid(struct edid *edid)
{
int i;
@@ -983,6 +1026,8 @@ void rk_edp_init(u32 vop_id)
val = (vop_id == 1) ? RK_SETBITS(1 << 5) : RK_CLRBITS(1 << 5);
writel(val, &rk3288_grf->soc_con6);
+ rockchip_edp_wait_hpd(&rk_edp);
+
rk_edp_init_refclk(&rk_edp);
rk_edp_init_interrupt(&rk_edp);
rk_edp_enable_sw_function(&rk_edp);
diff --git a/src/soc/rockchip/rk3288/include/soc/grf.h b/src/soc/rockchip/rk3288/include/soc/grf.h
index 832563830..9126aed83 100644
--- a/src/soc/rockchip/rk3288/include/soc/grf.h
+++ b/src/soc/rockchip/rk3288/include/soc/grf.h
@@ -89,7 +89,10 @@ struct rk3288_grf_regs {
u32 iomux_pwm0;
u32 iomux_pwm1;
};
- u32 gpio7b_iomux;
+ union {
+ u32 gpio7b_iomux;
+ u32 iomux_edp_hotplug;
+ };
union {
u32 gpio7cl_iomux;
u32 iomux_i2c5sda;
@@ -217,4 +220,5 @@ static struct rk3288_sgrf_regs * const rk3288_sgrf = (void *)GRF_SECURE_BASE;
#define IOMUX_EMMCPWREN RK_CLRSETBITS(0x3 << 2, 0x2 << 2)
#define IOMUX_EMMCCMD RK_CLRSETBITS(0x3f, 2 << 4 | 2 << 2 | 2 << 0)
#define IOMUX_PWM1 RK_SETBITS(1 << 2)
+#define IOMUX_EDP_HOTPLUG RK_CLRSETBITS(0x3 << 6, 0x2 << 6)
#endif