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authorStefan Reinauer <reinauer@chromium.org>2013-05-14 13:32:33 -0700
committerStefan Reinauer <stefan.reinauer@coreboot.org>2013-07-10 02:41:23 +0200
commitb98dec032f0d8ee158e606bceef9766a905ad503 (patch)
treefce643a46c82ab71e3778a9c798fb4fac7702371
parent043eb0e35f93b41348eb69061a6aa0355ef544bc (diff)
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coreboot-b98dec032f0d8ee158e606bceef9766a905ad503.zip
samsung/exynos5250: unify code
It turns out that the exynos5-common code previously imported from u-boot is not common code at all but very specific to the 5250 and not compatible with the 5450. Hence, unify the directories exynos5250 and exynos5-common. We will try to factor out common code while progressing with the 5450 port. Change-Id: Iab595e66fcd01eda8365c96fb8bef896f7602f03 Signed-off-by: Stefan Reinauer <reinauer@google.com> Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3641 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
-rw-r--r--src/cpu/samsung/Makefile.inc1
-rw-r--r--src/cpu/samsung/exynos5-common/Makefile.inc24
-rw-r--r--src/cpu/samsung/exynos5-common/clk.h70
-rw-r--r--src/cpu/samsung/exynos5-common/cpu.h128
-rw-r--r--src/cpu/samsung/exynos5-common/gpio.h285
-rw-r--r--src/cpu/samsung/exynos5-common/power.h45
-rw-r--r--src/cpu/samsung/exynos5-common/spi.h102
-rw-r--r--src/cpu/samsung/exynos5-common/uart.h55
-rw-r--r--src/cpu/samsung/exynos5250/Makefile.inc21
-rw-r--r--src/cpu/samsung/exynos5250/adc.h (renamed from src/cpu/samsung/exynos5-common/adc.h)0
-rw-r--r--src/cpu/samsung/exynos5250/clk.h45
-rw-r--r--src/cpu/samsung/exynos5250/clock.c1
-rw-r--r--src/cpu/samsung/exynos5250/clock.h (renamed from src/cpu/samsung/exynos5-common/clock.h)0
-rw-r--r--src/cpu/samsung/exynos5250/clock_init.c1
-rw-r--r--src/cpu/samsung/exynos5250/cpu.c4
-rw-r--r--src/cpu/samsung/exynos5250/cpu.h100
-rw-r--r--src/cpu/samsung/exynos5250/cpu_info.c (renamed from src/cpu/samsung/exynos5-common/cpu_info.c)8
-rw-r--r--src/cpu/samsung/exynos5250/dmc_init_ddr3.c3
-rw-r--r--src/cpu/samsung/exynos5250/exynos-fb.c (renamed from src/cpu/samsung/exynos5-common/exynos-fb.c)6
-rw-r--r--src/cpu/samsung/exynos5250/exynos-tmu.c (renamed from src/cpu/samsung/exynos5-common/exynos-tmu.c)4
-rw-r--r--src/cpu/samsung/exynos5250/exynos-tmu.h (renamed from src/cpu/samsung/exynos5-common/exynos-tmu.h)0
-rw-r--r--src/cpu/samsung/exynos5250/exynos5-common.h (renamed from src/cpu/samsung/exynos5-common/exynos5-common.h)0
-rw-r--r--src/cpu/samsung/exynos5250/exynos5250-tmu.c2
-rw-r--r--src/cpu/samsung/exynos5250/gpio.c (renamed from src/cpu/samsung/exynos5-common/gpio.c)1
-rw-r--r--src/cpu/samsung/exynos5250/gpio.h236
-rw-r--r--src/cpu/samsung/exynos5250/i2c.c (renamed from src/cpu/samsung/exynos5-common/i2c.c)4
-rw-r--r--src/cpu/samsung/exynos5250/i2c.h (renamed from src/cpu/samsung/exynos5-common/i2c.h)0
-rw-r--r--src/cpu/samsung/exynos5250/pinmux.c2
-rw-r--r--src/cpu/samsung/exynos5250/power.c1
-rw-r--r--src/cpu/samsung/exynos5250/power.h19
-rw-r--r--src/cpu/samsung/exynos5250/pwm.c (renamed from src/cpu/samsung/exynos5-common/pwm.c)4
-rw-r--r--src/cpu/samsung/exynos5250/pwm.h (renamed from src/cpu/samsung/exynos5-common/pwm.h)0
-rw-r--r--src/cpu/samsung/exynos5250/reset.c (renamed from src/cpu/samsung/exynos5-common/reset.c)0
-rw-r--r--src/cpu/samsung/exynos5250/s5p-dp-core.h (renamed from src/cpu/samsung/exynos5-common/s5p-dp-core.h)6
-rw-r--r--src/cpu/samsung/exynos5250/s5p-dp-reg.c (renamed from src/cpu/samsung/exynos5-common/s5p-dp-reg.c)2
-rw-r--r--src/cpu/samsung/exynos5250/spi.c (renamed from src/cpu/samsung/exynos5-common/spi.c)0
-rw-r--r--src/cpu/samsung/exynos5250/spi.h14
-rw-r--r--src/cpu/samsung/exynos5250/sromc.c (renamed from src/cpu/samsung/exynos5-common/sromc.c)0
-rw-r--r--src/cpu/samsung/exynos5250/sromc.h (renamed from src/cpu/samsung/exynos5-common/sromc.h)0
-rw-r--r--src/cpu/samsung/exynos5250/timer.c (renamed from src/cpu/samsung/exynos5-common/timer.c)6
-rw-r--r--src/cpu/samsung/exynos5250/uart.c3
-rw-r--r--src/cpu/samsung/exynos5250/uart.h29
-rw-r--r--src/cpu/samsung/exynos5250/wakeup.c2
-rw-r--r--src/cpu/samsung/exynos5250/watchdog.h (renamed from src/cpu/samsung/exynos5-common/watchdog.h)0
-rw-r--r--src/cpu/samsung/exynos5250/wdt.c (renamed from src/cpu/samsung/exynos5-common/wdt.c)0
-rw-r--r--src/mainboard/google/snow/chromeos.c1
-rw-r--r--src/mainboard/google/snow/mainboard.c6
-rw-r--r--src/mainboard/google/snow/memory.c1
-rw-r--r--src/mainboard/google/snow/romstage.c2
-rw-r--r--src/mainboard/google/snow/wakeup.c2
50 files changed, 492 insertions, 754 deletions
diff --git a/src/cpu/samsung/Makefile.inc b/src/cpu/samsung/Makefile.inc
index 97e9aab14..91109834b 100644
--- a/src/cpu/samsung/Makefile.inc
+++ b/src/cpu/samsung/Makefile.inc
@@ -1,2 +1 @@
-subdirs-$(CONFIG_CPU_SAMSUNG_EXYNOS5) += exynos5-common
subdirs-$(CONFIG_CPU_SAMSUNG_EXYNOS5) += exynos5250
diff --git a/src/cpu/samsung/exynos5-common/Makefile.inc b/src/cpu/samsung/exynos5-common/Makefile.inc
deleted file mode 100644
index 633186344..000000000
--- a/src/cpu/samsung/exynos5-common/Makefile.inc
+++ /dev/null
@@ -1,24 +0,0 @@
-romstage-y += spi.c
-ramstage-y += spi.c
-bootblock-y += spi.c
-
-bootblock-y += gpio.c
-bootblock-$(CONFIG_EARLY_CONSOLE) += pwm.c
-bootblock-$(CONFIG_EARLY_CONSOLE) += timer.c
-
-romstage-y += pwm.c # needed by timer.c
-romstage-y += gpio.c
-romstage-y += timer.c
-romstage-y += i2c.c
-
-#romstage-y += wdt.c
-#romstage-y += sromc.c
-
-ramstage-y += cpu_info.c
-ramstage-y += pwm.c # needed by timer.c
-ramstage-y += timer.c
-ramstage-y += gpio.c
-ramstage-y += i2c.c
-ramstage-y += s5p-dp-reg.c
-ramstage-y += exynos-fb.c
-ramstage-y += exynos-tmu.c
diff --git a/src/cpu/samsung/exynos5-common/clk.h b/src/cpu/samsung/exynos5-common/clk.h
deleted file mode 100644
index 9de4f4551..000000000
--- a/src/cpu/samsung/exynos5-common/clk.h
+++ /dev/null
@@ -1,70 +0,0 @@
-/*
- * (C) Copyright 2012 The Chromium Authors
- * (C) Copyright 2010 Samsung Electronics
- * Minkyu Kang <mk7.kang@samsung.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
- */
-
-#ifndef __EXYNOS_COMMON_CLK_H_
-#define __EXYNOS_COMMON_CLK_H_
-
-#include <types.h>
-#include <stdint.h>
-
-enum periph_id;
-
-#define APLL 0
-#define MPLL 1
-#define EPLL 2
-#define HPLL 3
-#define VPLL 4
-#define BPLL 5
-
-enum pll_src_bit {
- SRC_MPLL = 6,
- SRC_EPLL,
- SRC_VPLL,
-};
-
-/* *
- * This structure is to store the src bit, div bit and prediv bit
- * positions of the peripheral clocks of the src and div registers
- */
-struct clk_bit_info {
- s8 src_bit; /* offset in register to clock source field */
- s8 n_src_bits; /* number of bits in 'src_bit' field */
- s8 div_bit;
- s8 prediv_bit;
-};
-
-unsigned long get_pll_clk(int pllreg);
-unsigned long get_arm_clk(void);
-unsigned long get_pwm_clk(void);
-unsigned long get_uart_clk(int dev_index);
-void set_mmc_clk(int dev_index, unsigned int div);
-
-/**
- * get the clk frequency of the required peripherial
- *
- * @param peripherial Peripherial id
- *
- * @return frequency of the peripherial clk
- */
-unsigned long clock_get_periph_rate(enum periph_id peripheral);
-
-#endif
diff --git a/src/cpu/samsung/exynos5-common/cpu.h b/src/cpu/samsung/exynos5-common/cpu.h
deleted file mode 100644
index 8856ddb71..000000000
--- a/src/cpu/samsung/exynos5-common/cpu.h
+++ /dev/null
@@ -1,128 +0,0 @@
-/*
- * (C) Copyright 2009-2010 Samsung Electronics
- * Minkyu Kang <mk7.kang@samsung.com>
- * Heungjun Kim <riverful.kim@samsung.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
- */
-
-#ifndef _EXYNOS_COMMON_CPU_H
-#define _EXYNOS_COMMON_CPU_H
-
-#define S5PC1XX_ADDR_BASE 0xE0000000
-
-/* S5PC100 */
-#define S5PC100_PRO_ID 0xE0000000
-#define S5PC100_CLOCK_BASE 0xE0100000
-#define S5PC100_GPIO_BASE 0xE0300000
-#define S5PC100_VIC0_BASE 0xE4000000
-#define S5PC100_VIC1_BASE 0xE4100000
-#define S5PC100_VIC2_BASE 0xE4200000
-#define S5PC100_DMC_BASE 0xE6000000
-#define S5PC100_SROMC_BASE 0xE7000000
-#define S5PC100_ONENAND_BASE 0xE7100000
-#define S5PC100_PWMTIMER_BASE 0xEA000000
-#define S5PC100_WATCHDOG_BASE 0xEA200000
-#define S5PC100_UART_BASE 0xEC000000
-#define S5PC100_MMC_BASE 0xED800000
-
-/* S5PC110 */
-#define S5PC110_PRO_ID 0xE0000000
-#define S5PC110_CLOCK_BASE 0xE0100000
-#define S5PC110_GPIO_BASE 0xE0200000
-#define S5PC110_PWMTIMER_BASE 0xE2500000
-#define S5PC110_WATCHDOG_BASE 0xE2700000
-#define S5PC110_UART_BASE 0xE2900000
-#define S5PC110_SROMC_BASE 0xE8000000
-#define S5PC110_MMC_BASE 0xEB000000
-#define S5PC110_DMC0_BASE 0xF0000000
-#define S5PC110_DMC1_BASE 0xF1400000
-#define S5PC110_VIC0_BASE 0xF2000000
-#define S5PC110_VIC1_BASE 0xF2100000
-#define S5PC110_VIC2_BASE 0xF2200000
-#define S5PC110_VIC3_BASE 0xF2300000
-#define S5PC110_OTG_BASE 0xEC000000
-#define S5PC110_PHY_BASE 0xEC100000
-#define S5PC110_USB_PHY_CONTROL 0xE010E80C
-
-
-#include <arch/io.h>
-
-#define DEVICE_NOT_AVAILABLE 0
-
-#define EXYNOS_PRO_ID 0x10000000
-
-/* Address of address of function that copys data from SD or MMC */
-#define EXYNOS_COPY_MMC_FNPTR_ADDR 0x02020030
-
-/* Address of address of function that copys data from SPI */
-#define EXYNOS_COPY_SPI_FNPTR_ADDR 0x02020058
-
-/* Address of address of function that copys data through USB */
-#define EXYNOS_COPY_USB_FNPTR_ADDR 0x02020070
-
-/* Boot mode values */
-#define EXYNOS_USB_SECONDARY_BOOT 0xfeed0002
-
-#define EXYNOS_IRAM_SECONDARY_BASE 0x02020018
-
-#define EXYNOS_I2C_SPACING 0x10000
-
-enum boot_mode {
- /*
- * Assign the OM pin values for respective boot modes.
- * Exynos4 does not support spi boot and the mmc boot OM
- * pin values are the same across Exynos4 and Exynos5.
- */
- BOOT_MODE_MMC = 4,
- BOOT_MODE_SERIAL = 20,
- /* Boot based on Operating Mode pin settings */
- BOOT_MODE_OM = 32,
- BOOT_MODE_USB, /* Boot using USB download */
-};
-
-/**
- * Get the boot device containing BL1, BL2 (SPL) and U-boot
- *
- * @return boot device
- */
-enum boot_mode exynos_get_boot_device(void);
-
-/**
- * Check if a wakeup is permitted.
- *
- * On some boards we need to look at a special GPIO to ensure that the wakeup
- * from sleep was valid. If the wakeup is not valid we need to go through a
- * full reset.
- *
- * The default implementation of this function allows all wakeups.
- *
- * @return 1 if wakeup is permitted; 0 otherwise
- */
-int board_wakeup_permitted(void);
-
-/**
- * Init subsystems according to the reset status
- *
- * @return 0 for a normal boot, non-zero for a resume
- */
-int lowlevel_init_subsystems(void);
-
-int arch_cpu_init(void);
-
-
-#endif /* _EXYNOS_COMMON_CPU_H */
diff --git a/src/cpu/samsung/exynos5-common/gpio.h b/src/cpu/samsung/exynos5-common/gpio.h
deleted file mode 100644
index 0e4afc50c..000000000
--- a/src/cpu/samsung/exynos5-common/gpio.h
+++ /dev/null
@@ -1,285 +0,0 @@
-/*
- * (C) Copyright 2009-2010 Samsung Electronics
- * Minkyu Kang <mk7.kang@samsung.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __ASM_ARCH_COMMON_GPIO_H
-#define __ASM_ARCH_COMMON_GPIO_H
-
-#ifndef __ASSEMBLER__ /* FIXME: not needed (i hope)? */
-
-#include <cpu/samsung/exynos5-common/cpu.h> /* FIXME: for S5PC110_GPIO_BASE */
-
-struct s5p_gpio_bank {
- unsigned int con;
- unsigned int dat;
- unsigned int pull;
- unsigned int drv;
- unsigned int pdn_con;
- unsigned int pdn_pull;
- unsigned char res1[8];
-};
-
-struct s5pc100_gpio {
- struct s5p_gpio_bank a0;
- struct s5p_gpio_bank a1;
- struct s5p_gpio_bank b;
- struct s5p_gpio_bank c;
- struct s5p_gpio_bank d;
- struct s5p_gpio_bank e0;
- struct s5p_gpio_bank e1;
- struct s5p_gpio_bank f0;
- struct s5p_gpio_bank f1;
- struct s5p_gpio_bank f2;
- struct s5p_gpio_bank f3;
- struct s5p_gpio_bank g0;
- struct s5p_gpio_bank g1;
- struct s5p_gpio_bank g2;
- struct s5p_gpio_bank g3;
- struct s5p_gpio_bank i;
- struct s5p_gpio_bank j0;
- struct s5p_gpio_bank j1;
- struct s5p_gpio_bank j2;
- struct s5p_gpio_bank j3;
- struct s5p_gpio_bank j4;
- struct s5p_gpio_bank k0;
- struct s5p_gpio_bank k1;
- struct s5p_gpio_bank k2;
- struct s5p_gpio_bank k3;
- struct s5p_gpio_bank l0;
- struct s5p_gpio_bank l1;
- struct s5p_gpio_bank l2;
- struct s5p_gpio_bank l3;
- struct s5p_gpio_bank l4;
- struct s5p_gpio_bank h0;
- struct s5p_gpio_bank h1;
- struct s5p_gpio_bank h2;
- struct s5p_gpio_bank h3;
-};
-
-struct s5pc110_gpio {
- struct s5p_gpio_bank a0;
- struct s5p_gpio_bank a1;
- struct s5p_gpio_bank b;
- struct s5p_gpio_bank c0;
- struct s5p_gpio_bank c1;
- struct s5p_gpio_bank d0;
- struct s5p_gpio_bank d1;
- struct s5p_gpio_bank e0;
- struct s5p_gpio_bank e1;
- struct s5p_gpio_bank f0;
- struct s5p_gpio_bank f1;
- struct s5p_gpio_bank f2;
- struct s5p_gpio_bank f3;
- struct s5p_gpio_bank g0;
- struct s5p_gpio_bank g1;
- struct s5p_gpio_bank g2;
- struct s5p_gpio_bank g3;
- struct s5p_gpio_bank i;
- struct s5p_gpio_bank j0;
- struct s5p_gpio_bank j1;
- struct s5p_gpio_bank j2;
- struct s5p_gpio_bank j3;
- struct s5p_gpio_bank j4;
- struct s5p_gpio_bank mp0_1;
- struct s5p_gpio_bank mp0_2;
- struct s5p_gpio_bank mp0_3;
- struct s5p_gpio_bank mp0_4;
- struct s5p_gpio_bank mp0_5;
- struct s5p_gpio_bank mp0_6;
- struct s5p_gpio_bank mp0_7;
- struct s5p_gpio_bank mp1_0;
- struct s5p_gpio_bank mp1_1;
- struct s5p_gpio_bank mp1_2;
- struct s5p_gpio_bank mp1_3;
- struct s5p_gpio_bank mp1_4;
- struct s5p_gpio_bank mp1_5;
- struct s5p_gpio_bank mp1_6;
- struct s5p_gpio_bank mp1_7;
- struct s5p_gpio_bank mp1_8;
- struct s5p_gpio_bank mp2_0;
- struct s5p_gpio_bank mp2_1;
- struct s5p_gpio_bank mp2_2;
- struct s5p_gpio_bank mp2_3;
- struct s5p_gpio_bank mp2_4;
- struct s5p_gpio_bank mp2_5;
- struct s5p_gpio_bank mp2_6;
- struct s5p_gpio_bank mp2_7;
- struct s5p_gpio_bank mp2_8;
- struct s5p_gpio_bank res1[48];
- struct s5p_gpio_bank h0;
- struct s5p_gpio_bank h1;
- struct s5p_gpio_bank h2;
- struct s5p_gpio_bank h3;
-};
-
-/* functions */
-void s5p_gpio_cfg_pin(struct s5p_gpio_bank *bank, int gpio, int cfg);
-void s5p_gpio_direction_output(struct s5p_gpio_bank *bank, int gpio, int en);
-void s5p_gpio_direction_input(struct s5p_gpio_bank *bank, int gpio);
-void s5p_gpio_set_value(struct s5p_gpio_bank *bank, int gpio, int en);
-unsigned int s5p_gpio_get_value(struct s5p_gpio_bank *bank, int gpio);
-void s5p_gpio_set_pull(struct s5p_gpio_bank *bank, int gpio, int mode);
-void s5p_gpio_set_drv(struct s5p_gpio_bank *bank, int gpio, int mode);
-void s5p_gpio_set_rate(struct s5p_gpio_bank *bank, int gpio, int mode);
-
-/* GPIO pins per bank */
-#define GPIO_PER_BANK 8
-
-static inline unsigned int s5p_gpio_base(int nr)
-{
- return S5PC110_GPIO_BASE;
-}
-
-#define s5pc110_gpio_get_nr(bank, pin) \
- ((((((unsigned int)&(((struct s5pc110_gpio *)S5PC110_GPIO_BASE)->bank))\
- - S5PC110_GPIO_BASE) / sizeof(struct s5p_gpio_bank)) \
- * GPIO_PER_BANK) + pin)
-#endif
-
-/* Pin configurations */
-#define GPIO_INPUT 0x0
-#define GPIO_OUTPUT 0x1
-#define GPIO_IRQ 0xf
-#define GPIO_FUNC(x) (x)
-
-/* Pull mode */
-#define GPIO_PULL_NONE 0x0
-#define GPIO_PULL_DOWN 0x1
-#define GPIO_PULL_UP 0x2
-
-/* Drive Strength level */
-#define GPIO_DRV_1X 0x0
-#define GPIO_DRV_3X 0x1
-#define GPIO_DRV_2X 0x2
-#define GPIO_DRV_4X 0x3
-#define GPIO_DRV_FAST 0x0
-#define GPIO_DRV_SLOW 0x1
-
-#if 0
-struct s5p_gpio_bank {
- unsigned int con;
- unsigned int dat;
- unsigned int pull;
- unsigned int drv;
- unsigned int pdn_con;
- unsigned int pdn_pull;
- unsigned char res1[8];
-};
-
-/* functions */
-void s5p_gpio_cfg_pin(struct s5p_gpio_bank *bank, int gpio, int cfg);
-void s5p_gpio_direction_output(struct s5p_gpio_bank *bank, int gpio, int en);
-void s5p_gpio_direction_input(struct s5p_gpio_bank *bank, int gpio);
-void s5p_gpio_set_value(struct s5p_gpio_bank *bank, int gpio, int en);
-unsigned int s5p_gpio_get_value(struct s5p_gpio_bank *bank, int gpio);
-void s5p_gpio_set_pull(struct s5p_gpio_bank *bank, int gpio, int mode);
-void s5p_gpio_set_drv(struct s5p_gpio_bank *bank, int gpio, int mode);
-void s5p_gpio_set_rate(struct s5p_gpio_bank *bank, int gpio, int mode);
-#endif
-
-/* GPIO pins per bank */
-#define GPIO_PER_BANK 8
-
-/* Pin configurations */
-#define EXYNOS_GPIO_INPUT 0x0
-#define EXYNOS_GPIO_OUTPUT 0x1
-#define EXYNOS_GPIO_IRQ 0xf
-#define EXYNOS_GPIO_FUNC(x) (x)
-
-/* Pull mode */
-#define EXYNOS_GPIO_PULL_NONE 0x0
-#define EXYNOS_GPIO_PULL_DOWN 0x1
-#define EXYNOS_GPIO_PULL_UP 0x3
-
-/* Drive Strength level */
-#define EXYNOS_GPIO_DRV_1X 0x0
-#define EXYNOS_GPIO_DRV_3X 0x1
-#define EXYNOS_GPIO_DRV_2X 0x2
-#define EXYNOS_GPIO_DRV_4X 0x3
-#define EXYNOS_GPIO_DRV_FAST 0x0
-#define EXYNOS_GPIO_DRV_SLOW 0x1
-
-#define EXYNOS5_GPIO_BASE0 0x11400000
-#define EXYNOS5_GPIO_BASE1 0x13400000
-#define EXYNOS5_GPIO_BASE2 0x10d10000
-#define EXYNOS5_GPIO_BASE3 0x03860000
-
-enum exynos5_gpio_port {
- /*
- * Ordered by base address + offset.
- * ETC registers are special, thus not included.
- */
-
- /* base == EXYNOS_GPIO_BASE0 */
- EXYNOS5_GPA0 = EXYNOS5_GPIO_BASE0 + 0x0000,
- EXYNOS5_GPA1 = EXYNOS5_GPIO_BASE0 + 0x0020,
- EXYNOS5_GPA2 = EXYNOS5_GPIO_BASE0 + 0x0040,
-
- EXYNOS5_GPB0 = EXYNOS5_GPIO_BASE0 + 0x0060,
- EXYNOS5_GPB1 = EXYNOS5_GPIO_BASE0 + 0x0080,
- EXYNOS5_GPB2 = EXYNOS5_GPIO_BASE0 + 0x00a0,
- EXYNOS5_GPB3 = EXYNOS5_GPIO_BASE0 + 0x00c0,
-
- EXYNOS5_GPC0 = EXYNOS5_GPIO_BASE0 + 0x00e0,
- EXYNOS5_GPC1 = EXYNOS5_GPIO_BASE0 + 0x0100,
- EXYNOS5_GPC2 = EXYNOS5_GPIO_BASE0 + 0x0120,
- EXYNOS5_GPC3 = EXYNOS5_GPIO_BASE0 + 0x0140,
-
- EXYNOS5_GPD0 = EXYNOS5_GPIO_BASE0 + 0x0160,
- EXYNOS5_GPD1 = EXYNOS5_GPIO_BASE0 + 0x0180,
-
- EXYNOS5_GPY0 = EXYNOS5_GPIO_BASE0 + 0x01a0,
- EXYNOS5_GPY1 = EXYNOS5_GPIO_BASE0 + 0x01c0,
- EXYNOS5_GPY2 = EXYNOS5_GPIO_BASE0 + 0x01e0,
- EXYNOS5_GPY3 = EXYNOS5_GPIO_BASE0 + 0x0200,
- EXYNOS5_GPY4 = EXYNOS5_GPIO_BASE0 + 0x0220,
- EXYNOS5_GPY5 = EXYNOS5_GPIO_BASE0 + 0x0240,
- EXYNOS5_GPY6 = EXYNOS5_GPIO_BASE0 + 0x0260,
-
- EXYNOS5_GPX0 = EXYNOS5_GPIO_BASE0 + 0x0c00,
- EXYNOS5_GPX1 = EXYNOS5_GPIO_BASE0 + 0x0c20,
- EXYNOS5_GPX2 = EXYNOS5_GPIO_BASE0 + 0x0c40,
- EXYNOS5_GPX3 = EXYNOS5_GPIO_BASE0 + 0x0c60,
-
- /* base == EXYNOS_GPIO_BASE1 */
- EXYNOS5_GPE0 = EXYNOS5_GPIO_BASE1 + 0x0000,
- EXYNOS5_GPE1 = EXYNOS5_GPIO_BASE1 + 0x0020,
-
- EXYNOS5_GPF0 = EXYNOS5_GPIO_BASE1 + 0x0040,
- EXYNOS5_GPF1 = EXYNOS5_GPIO_BASE1 + 0x0060,
-
- EXYNOS5_GPG0 = EXYNOS5_GPIO_BASE1 + 0x0080,
- EXYNOS5_GPG1 = EXYNOS5_GPIO_BASE1 + 0x00a0,
- EXYNOS5_GPG2 = EXYNOS5_GPIO_BASE1 + 0x00c0,
-
- EXYNOS5_GPH0 = EXYNOS5_GPIO_BASE1 + 0x00e0,
- EXYNOS5_GPH1 = EXYNOS5_GPIO_BASE1 + 0x0100,
-
- /* base == EXYNOS_GPIO_BASE2 */
- EXYNOS5_GPV0 = EXYNOS5_GPIO_BASE2 + 0x0000,
- EXYNOS5_GPV1 = EXYNOS5_GPIO_BASE2 + 0x0020,
- EXYNOS5_GPV2 = EXYNOS5_GPIO_BASE2 + 0x0060,
- EXYNOS5_GPV3 = EXYNOS5_GPIO_BASE2 + 0x0080,
- EXYNOS5_GPV4 = EXYNOS5_GPIO_BASE2 + 0x00c0,
-
- /* base == EXYNOS_GPIO_BASE3 */
- EXYNOS5_GPZ = EXYNOS5_GPIO_BASE3 + 0x0000,
-};
-
-#endif
diff --git a/src/cpu/samsung/exynos5-common/power.h b/src/cpu/samsung/exynos5-common/power.h
deleted file mode 100644
index ff98123d6..000000000
--- a/src/cpu/samsung/exynos5-common/power.h
+++ /dev/null
@@ -1,45 +0,0 @@
-/*
- * Copyright (c) 2009 Samsung Electronics
- * Kyungmin Park <kyungmin.park@samsung.com>
- * Minkyu Kang <mk7.kang@samsung.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
- */
-
-#ifndef __ASM_ARM_ARCH_POWER_H_
-#define __ASM_ARM_ARCH_POWER_H_
-
-/*
- * Power control
- */
-#define S5PC100_OTHERS 0xE0108200
-#define S5PC100_RST_STAT 0xE0108300
-#define S5PC100_SLEEP_WAKEUP (1 << 3)
-#define S5PC100_WAKEUP_STAT 0xE0108304
-#define S5PC100_INFORM0 0xE0108400
-
-#define S5PC110_RST_STAT 0xE010A000
-#define S5PC110_SLEEP_WAKEUP (1 << 3)
-#define S5PC110_WAKEUP_STAT 0xE010C200
-#define S5PC110_OTHERS 0xE010E000
-#define S5PC110_USB_PHY_CON 0xE010E80C
-#define S5PC110_INFORM0 0xE010F000
-
-/* Enable HW thermal trip with PS_HOLD_CONTROL register ENABLE_HW_TRIP bit */
-void power_enable_hw_thermal_trip(void);
-
-#endif
diff --git a/src/cpu/samsung/exynos5-common/spi.h b/src/cpu/samsung/exynos5-common/spi.h
deleted file mode 100644
index 156817c35..000000000
--- a/src/cpu/samsung/exynos5-common/spi.h
+++ /dev/null
@@ -1,102 +0,0 @@
-/*
- * (C) Copyright 2012 SAMSUNG Electronics
- * Padmavathi Venna <padma.v@samsung.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- */
-
-#ifndef __ASM_ARCH_EXYNOS_COMMON_SPI_H_
-#define __ASM_ARCH_EXYNOS_COMMON_SPI_H_
-
-#ifndef __ASSEMBLER__
-
-// This driver serves as a CBFS media source.
-#include <cbfs.h>
-
-/* SPI peripheral register map; padded to 64KB */
-struct exynos_spi {
- unsigned int ch_cfg; /* 0x00 */
- unsigned char reserved0[4];
- unsigned int mode_cfg; /* 0x08 */
- unsigned int cs_reg; /* 0x0c */
- unsigned char reserved1[4];
- unsigned int spi_sts; /* 0x14 */
- unsigned int tx_data; /* 0x18 */
- unsigned int rx_data; /* 0x1c */
- unsigned int pkt_cnt; /* 0x20 */
- unsigned char reserved2[4];
- unsigned int swap_cfg; /* 0x28 */
- unsigned int fb_clk; /* 0x2c */
- unsigned char padding[0xffd0];
-};
-
-#define EXYNOS_SPI_MAX_FREQ 50000000
-
-#define SPI_TIMEOUT_MS 10
-
-#define SF_READ_DATA_CMD 0x3
-
-/* SPI_CHCFG */
-#define SPI_CH_HS_EN (1 << 6)
-#define SPI_CH_RST (1 << 5)
-#define SPI_SLAVE_MODE (1 << 4)
-#define SPI_CH_CPOL_L (1 << 3)
-#define SPI_CH_CPHA_B (1 << 2)
-#define SPI_RX_CH_ON (1 << 1)
-#define SPI_TX_CH_ON (1 << 0)
-
-/* SPI_MODECFG */
-#define SPI_MODE_CH_WIDTH_WORD (0x2 << 29)
-#define SPI_MODE_BUS_WIDTH_WORD (0x2 << 17)
-
-/* SPI_CSREG */
-#define SPI_SLAVE_SIG_INACT (1 << 0)
-
-/* SPI_STS */
-#define SPI_ST_TX_DONE (1 << 25)
-#define SPI_FIFO_LVL_MASK 0x1ff
-#define SPI_TX_LVL_OFFSET 6
-#define SPI_RX_LVL_OFFSET 15
-
-/* Feedback Delay */
-#define SPI_CLK_BYPASS (0 << 0)
-#define SPI_FB_DELAY_90 (1 << 0)
-#define SPI_FB_DELAY_180 (2 << 0)
-#define SPI_FB_DELAY_270 (3 << 0)
-
-/* Packet Count */
-#define SPI_PACKET_CNT_EN (1 << 16)
-
-/* Swap config */
-#define SPI_TX_SWAP_EN (1 << 0)
-#define SPI_TX_BYTE_SWAP (1 << 2)
-#define SPI_TX_HWORD_SWAP (1 << 3)
-#define SPI_TX_BYTE_SWAP (1 << 2)
-#define SPI_RX_SWAP_EN (1 << 4)
-#define SPI_RX_BYTE_SWAP (1 << 6)
-#define SPI_RX_HWORD_SWAP (1 << 7)
-
-/* API */
-int exynos_spi_open(struct exynos_spi *regs);
-int exynos_spi_read(struct exynos_spi *regs, void *dest, u32 len, u32 off);
-int exynos_spi_close(struct exynos_spi *regs);
-
-/* Serve as CBFS Media */
-int initialize_exynos_spi_cbfs_media(struct cbfs_media *media,
- void *buffer_address,
- size_t buffer_size);
-
-#endif /* __ASSEMBLER__ */
-#endif
diff --git a/src/cpu/samsung/exynos5-common/uart.h b/src/cpu/samsung/exynos5-common/uart.h
deleted file mode 100644
index 350e224b8..000000000
--- a/src/cpu/samsung/exynos5-common/uart.h
+++ /dev/null
@@ -1,55 +0,0 @@
-/*
- * (C) Copyright 2009 Samsung Electronics
- * Minkyu Kang <mk7.kang@samsung.com>
- * Heungjun Kim <riverful.kim@samsung.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
- */
-
-#ifndef __EXYNOS_COMMON_UART_H_
-#define __EXYNOS_COMMON_UART_H_
-
-/* baudrate rest value */
-union br_rest {
- unsigned short slot; /* udivslot */
- unsigned char value; /* ufracval */
-};
-
-struct s5p_uart {
- unsigned int ulcon;
- unsigned int ucon;
- unsigned int ufcon;
- unsigned int umcon;
- unsigned int utrstat;
- unsigned int uerstat;
- unsigned int ufstat;
- unsigned int umstat;
- unsigned char utxh;
- unsigned char res1[3];
- unsigned char urxh;
- unsigned char res2[3];
- unsigned int ubrdiv;
- union br_rest rest;
- unsigned char res3[0xffd0];
-};
-
-static inline int s5p_uart_divslot(void)
-{
- return 0;
-}
-
-#endif
diff --git a/src/cpu/samsung/exynos5250/Makefile.inc b/src/cpu/samsung/exynos5250/Makefile.inc
index 6449714a5..d89bc95ce 100644
--- a/src/cpu/samsung/exynos5250/Makefile.inc
+++ b/src/cpu/samsung/exynos5250/Makefile.inc
@@ -3,6 +3,7 @@
# image outside of CBFS
INTERMEDIATE += exynos5250_add_bl1
+bootblock-y += spi.c
bootblock-y += pinmux.c mct.c power.c
# Clock is required for UART
bootblock-$(CONFIG_EARLY_CONSOLE) += clock_init.c
@@ -11,7 +12,11 @@ bootblock-$(CONFIG_EARLY_CONSOLE) += monotonic_timer.c
bootblock-$(CONFIG_EARLY_CONSOLE) += soc.c
bootblock-$(CONFIG_EARLY_CONSOLE) += uart.c
bootblock-y += wakeup.c
+bootblock-y += gpio.c
+bootblock-$(CONFIG_EARLY_CONSOLE) += pwm.c
+bootblock-$(CONFIG_EARLY_CONSOLE) += timer.c
+romstage-y += spi.c
romstage-y += clock.c
romstage-y += clock_init.c
romstage-y += pinmux.c # required by s3c24x0_i2c (exynos5-common) and uart.
@@ -23,7 +28,14 @@ romstage-y += monotonic_timer.c
romstage-$(CONFIG_EARLY_CONSOLE) += soc.c
romstage-$(CONFIG_EARLY_CONSOLE) += uart.c
romstage-y += wakeup.c
+romstage-y += pwm.c # needed by timer.c
+romstage-y += gpio.c
+romstage-y += timer.c
+romstage-y += i2c.c
+#romstage-y += wdt.c
+#romstage-y += sromc.c
+ramstage-y += spi.c
#ramstage-y += tzpc_init.c
ramstage-y += clock.c
ramstage-y += clock_init.c
@@ -35,8 +47,15 @@ ramstage-y += cpu.c
ramstage-y += exynos5250-tmu.c
ramstage-y += mct.c
ramstage-y += monotonic_timer.c
-
#ramstage-$(CONFIG_SATA_AHCI) += sata.c
+ramstage-y += cpu_info.c
+ramstage-y += pwm.c # needed by timer.c
+ramstage-y += timer.c
+ramstage-y += gpio.c
+ramstage-y += i2c.c
+ramstage-y += s5p-dp-reg.c
+ramstage-y += exynos-fb.c
+ramstage-y += exynos-tmu.c
exynos5250_add_bl1: $(obj)/coreboot.pre
printf " DD Adding Samsung Exynos5250 BL1\n"
diff --git a/src/cpu/samsung/exynos5-common/adc.h b/src/cpu/samsung/exynos5250/adc.h
index 64f481349..64f481349 100644
--- a/src/cpu/samsung/exynos5-common/adc.h
+++ b/src/cpu/samsung/exynos5250/adc.h
diff --git a/src/cpu/samsung/exynos5250/clk.h b/src/cpu/samsung/exynos5250/clk.h
index 828e7d883..24e8e7066 100644
--- a/src/cpu/samsung/exynos5250/clk.h
+++ b/src/cpu/samsung/exynos5250/clk.h
@@ -22,7 +22,50 @@
#ifndef __EXYNOS5_CLK_H__
#define __EXYNOS5_CLK_H__
-#include <cpu/samsung/exynos5-common/clk.h>
+#include <types.h>
+#include <stdint.h>
+
+enum periph_id;
+
+#define APLL 0
+#define MPLL 1
+#define EPLL 2
+#define HPLL 3
+#define VPLL 4
+#define BPLL 5
+
+enum pll_src_bit {
+ SRC_MPLL = 6,
+ SRC_EPLL,
+ SRC_VPLL,
+};
+
+/* *
+ * This structure is to store the src bit, div bit and prediv bit
+ * positions of the peripheral clocks of the src and div registers
+ */
+struct clk_bit_info {
+ s8 src_bit; /* offset in register to clock source field */
+ s8 n_src_bits; /* number of bits in 'src_bit' field */
+ s8 div_bit;
+ s8 prediv_bit;
+};
+
+unsigned long get_pll_clk(int pllreg);
+unsigned long get_arm_clk(void);
+unsigned long get_pwm_clk(void);
+unsigned long get_uart_clk(int dev_index);
+void set_mmc_clk(int dev_index, unsigned int div);
+
+/**
+ * get the clk frequency of the required peripherial
+ *
+ * @param peripherial Peripherial id
+ *
+ * @return frequency of the peripherial clk
+ */
+unsigned long clock_get_periph_rate(enum periph_id peripheral);
+
#include <cpu/samsung/exynos5250/pinmux.h>
diff --git a/src/cpu/samsung/exynos5250/clock.c b/src/cpu/samsung/exynos5250/clock.c
index 3622e2835..de41346fa 100644
--- a/src/cpu/samsung/exynos5250/clock.c
+++ b/src/cpu/samsung/exynos5250/clock.c
@@ -29,7 +29,6 @@
#include <cpu/samsung/exynos5250/clk.h>
#include <cpu/samsung/exynos5250/clock_init.h>
#include <cpu/samsung/exynos5250/cpu.h>
-#include <cpu/samsung/exynos5-common/clk.h>
/* input clock of PLL: SMDK5250 has 24MHz input clock */
#define CONFIG_SYS_CLK_FREQ 24000000
diff --git a/src/cpu/samsung/exynos5-common/clock.h b/src/cpu/samsung/exynos5250/clock.h
index c0cd896b2..c0cd896b2 100644
--- a/src/cpu/samsung/exynos5-common/clock.h
+++ b/src/cpu/samsung/exynos5250/clock.h
diff --git a/src/cpu/samsung/exynos5250/clock_init.c b/src/cpu/samsung/exynos5250/clock_init.c
index 0989b88bb..42ff9adbd 100644
--- a/src/cpu/samsung/exynos5250/clock_init.c
+++ b/src/cpu/samsung/exynos5250/clock_init.c
@@ -34,7 +34,6 @@
#include <cpu/samsung/exynos5250/cpu.h>
#include <cpu/samsung/exynos5250/dmc.h>
#include <cpu/samsung/exynos5250/s5p-dp.h>
-#include <cpu/samsung/exynos5-common/clk.h>
#include "setup.h"
diff --git a/src/cpu/samsung/exynos5250/cpu.c b/src/cpu/samsung/exynos5250/cpu.c
index c49dec453..2acebbb6e 100644
--- a/src/cpu/samsung/exynos5250/cpu.c
+++ b/src/cpu/samsung/exynos5250/cpu.c
@@ -7,8 +7,8 @@
#include <cbmem.h>
#include <arch/cache.h>
#include <cpu/samsung/exynos5250/fimd.h>
-#include <cpu/samsung/exynos5-common/s5p-dp-core.h>
-#include <cpu/samsung/exynos5-common/cpu.h>
+#include <cpu/samsung/exynos5250/s5p-dp-core.h>
+#include <cpu/samsung/exynos5250/cpu.h>
#include "chip.h"
#include "cpu.h"
diff --git a/src/cpu/samsung/exynos5250/cpu.h b/src/cpu/samsung/exynos5250/cpu.h
index cff966ee9..1f94d8f98 100644
--- a/src/cpu/samsung/exynos5250/cpu.h
+++ b/src/cpu/samsung/exynos5250/cpu.h
@@ -22,7 +22,105 @@
#ifndef _EXYNOS5250_CPU_H
#define _EXYNOS5250_CPU_H
-#include <cpu/samsung/exynos5-common/cpu.h>
+#define S5PC1XX_ADDR_BASE 0xE0000000
+
+/* S5PC100 */
+#define S5PC100_PRO_ID 0xE0000000
+#define S5PC100_CLOCK_BASE 0xE0100000
+#define S5PC100_GPIO_BASE 0xE0300000
+#define S5PC100_VIC0_BASE 0xE4000000
+#define S5PC100_VIC1_BASE 0xE4100000
+#define S5PC100_VIC2_BASE 0xE4200000
+#define S5PC100_DMC_BASE 0xE6000000
+#define S5PC100_SROMC_BASE 0xE7000000
+#define S5PC100_ONENAND_BASE 0xE7100000
+#define S5PC100_PWMTIMER_BASE 0xEA000000
+#define S5PC100_WATCHDOG_BASE 0xEA200000
+#define S5PC100_UART_BASE 0xEC000000
+#define S5PC100_MMC_BASE 0xED800000
+
+/* S5PC110 */
+#define S5PC110_PRO_ID 0xE0000000
+#define S5PC110_CLOCK_BASE 0xE0100000
+#define S5PC110_GPIO_BASE 0xE0200000
+#define S5PC110_PWMTIMER_BASE 0xE2500000
+#define S5PC110_WATCHDOG_BASE 0xE2700000
+#define S5PC110_UART_BASE 0xE2900000
+#define S5PC110_SROMC_BASE 0xE8000000
+#define S5PC110_MMC_BASE 0xEB000000
+#define S5PC110_DMC0_BASE 0xF0000000
+#define S5PC110_DMC1_BASE 0xF1400000
+#define S5PC110_VIC0_BASE 0xF2000000
+#define S5PC110_VIC1_BASE 0xF2100000
+#define S5PC110_VIC2_BASE 0xF2200000
+#define S5PC110_VIC3_BASE 0xF2300000
+#define S5PC110_OTG_BASE 0xEC000000
+#define S5PC110_PHY_BASE 0xEC100000
+#define S5PC110_USB_PHY_CONTROL 0xE010E80C
+
+#include <arch/io.h>
+
+#define DEVICE_NOT_AVAILABLE 0
+
+#define EXYNOS_PRO_ID 0x10000000
+
+/* Address of address of function that copys data from SD or MMC */
+#define EXYNOS_COPY_MMC_FNPTR_ADDR 0x02020030
+
+/* Address of address of function that copys data from SPI */
+#define EXYNOS_COPY_SPI_FNPTR_ADDR 0x02020058
+
+/* Address of address of function that copys data through USB */
+#define EXYNOS_COPY_USB_FNPTR_ADDR 0x02020070
+
+/* Boot mode values */
+#define EXYNOS_USB_SECONDARY_BOOT 0xfeed0002
+
+#define EXYNOS_IRAM_SECONDARY_BASE 0x02020018
+
+#define EXYNOS_I2C_SPACING 0x10000
+
+enum boot_mode {
+ /*
+ * Assign the OM pin values for respective boot modes.
+ * Exynos4 does not support spi boot and the mmc boot OM
+ * pin values are the same across Exynos4 and Exynos5.
+ */
+ BOOT_MODE_MMC = 4,
+ BOOT_MODE_SERIAL = 20,
+ /* Boot based on Operating Mode pin settings */
+ BOOT_MODE_OM = 32,
+ BOOT_MODE_USB, /* Boot using USB download */
+};
+
+/**
+ * Get the boot device containing BL1, BL2 (SPL) and U-boot
+ *
+ * @return boot device
+ */
+enum boot_mode exynos_get_boot_device(void);
+
+/**
+ * Check if a wakeup is permitted.
+ *
+ * On some boards we need to look at a special GPIO to ensure that the wakeup
+ * from sleep was valid. If the wakeup is not valid we need to go through a
+ * full reset.
+ *
+ * The default implementation of this function allows all wakeups.
+ *
+ * @return 1 if wakeup is permitted; 0 otherwise
+ */
+int board_wakeup_permitted(void);
+
+/**
+ * Init subsystems according to the reset status
+ *
+ * @return 0 for a normal boot, non-zero for a resume
+ */
+int lowlevel_init_subsystems(void);
+
+int arch_cpu_init(void);
/* EXYNOS5 */
#define EXYNOS5_GPIO_PART6_BASE 0x03860000 /* Z<6:0> */
diff --git a/src/cpu/samsung/exynos5-common/cpu_info.c b/src/cpu/samsung/exynos5250/cpu_info.c
index ca9454ef6..498ed85a1 100644
--- a/src/cpu/samsung/exynos5-common/cpu_info.c
+++ b/src/cpu/samsung/exynos5250/cpu_info.c
@@ -25,12 +25,10 @@
#include <common.h>
#include <arch/io.h>
-#include <cpu/samsung/exynos5-common/clk.h>
-#include <cpu/samsung/exynos5-common/clock.h>
-#include <cpu/samsung/exynos5-common/cpu.h>
-
+#include <cpu/samsung/exynos5250/clk.h>
+#include <cpu/samsung/exynos5250/clock.h>
+#include <cpu/samsung/exynos5250/cpu.h>
#include <cpu/samsung/exynos5250/dmc.h>
-#include <cpu/samsung/exynos5-common/cpu.h> /* for EXYNOS_PRO_ID */
/* FIXME(dhendrix): consolidate samsung ID code/#defines to a common location */
#include <cpu/samsung/exynos5250/setup.h> /* cpu_info_init() prototype */
diff --git a/src/cpu/samsung/exynos5250/dmc_init_ddr3.c b/src/cpu/samsung/exynos5250/dmc_init_ddr3.c
index 132471de7..3dc9b47dd 100644
--- a/src/cpu/samsung/exynos5250/dmc_init_ddr3.c
+++ b/src/cpu/samsung/exynos5250/dmc_init_ddr3.c
@@ -26,9 +26,8 @@
#include <delay.h>
#include <arch/io.h>
#include <console/console.h>
-//#include "clock.h"
/* FIXME(dhendrix): untangle clock/clk ... */
-#include <cpu/samsung/exynos5-common/clock.h>
+#include <cpu/samsung/exynos5250/clock.h>
#include "clk.h"
#include "cpu.h"
#include "dmc.h"
diff --git a/src/cpu/samsung/exynos5-common/exynos-fb.c b/src/cpu/samsung/exynos5250/exynos-fb.c
index b2e926f77..5b6712028 100644
--- a/src/cpu/samsung/exynos5-common/exynos-fb.c
+++ b/src/cpu/samsung/exynos5250/exynos-fb.c
@@ -35,7 +35,7 @@
#include <drivers/maxim/max77686/max77686.h>
#include "device/i2c.h"
-#include "cpu/samsung/exynos5-common/i2c.h"
+#include "cpu/samsung/exynos5250/i2c.h"
#include "cpu/samsung/exynos5250/dsim.h"
#include "cpu/samsung/exynos5250/fimd.h"
@@ -85,8 +85,8 @@ enum {
ERR_NO_FDT_NODE,
};
-/* ok, this is stupid, but we're going to leave the variables in here until we know it works.
- * one cleanup task at a time.
+/* ok, this is stupid, but we're going to leave the variables in here until we
+ * know it works. One cleanup task at a time.
*/
enum stage_t {
STAGE_START = 0,
diff --git a/src/cpu/samsung/exynos5-common/exynos-tmu.c b/src/cpu/samsung/exynos5250/exynos-tmu.c
index 26777fca2..2bd959c9e 100644
--- a/src/cpu/samsung/exynos5-common/exynos-tmu.c
+++ b/src/cpu/samsung/exynos5250/exynos-tmu.c
@@ -19,8 +19,8 @@
*/
#include <arch/io.h>
-#include <cpu/samsung/exynos5-common/power.h>
-#include <cpu/samsung/exynos5-common/exynos-tmu.h>
+#include <cpu/samsung/exynos5250/power.h>
+#include <cpu/samsung/exynos5250/exynos-tmu.h>
#include <console/console.h>
diff --git a/src/cpu/samsung/exynos5-common/exynos-tmu.h b/src/cpu/samsung/exynos5250/exynos-tmu.h
index 40eda5626..40eda5626 100644
--- a/src/cpu/samsung/exynos5-common/exynos-tmu.h
+++ b/src/cpu/samsung/exynos5250/exynos-tmu.h
diff --git a/src/cpu/samsung/exynos5-common/exynos5-common.h b/src/cpu/samsung/exynos5250/exynos5-common.h
index b2957bfc6..b2957bfc6 100644
--- a/src/cpu/samsung/exynos5-common/exynos5-common.h
+++ b/src/cpu/samsung/exynos5250/exynos5-common.h
diff --git a/src/cpu/samsung/exynos5250/exynos5250-tmu.c b/src/cpu/samsung/exynos5250/exynos5250-tmu.c
index 7d8397c56..248968b9b 100644
--- a/src/cpu/samsung/exynos5250/exynos5250-tmu.c
+++ b/src/cpu/samsung/exynos5250/exynos5250-tmu.c
@@ -22,7 +22,7 @@
* This file contains Exynos5250-specific TMU information.
*/
-#include <cpu/samsung/exynos5-common/exynos-tmu.h>
+#include <cpu/samsung/exynos5250/exynos-tmu.h>
#include <cpu/samsung/exynos5250/cpu.h>
struct tmu_info exynos5250_tmu_info = {
diff --git a/src/cpu/samsung/exynos5-common/gpio.c b/src/cpu/samsung/exynos5250/gpio.c
index c9c4c26ce..853fa6fe7 100644
--- a/src/cpu/samsung/exynos5-common/gpio.c
+++ b/src/cpu/samsung/exynos5250/gpio.c
@@ -25,7 +25,6 @@
#include <gpio.h>
#include <arch/gpio.h>
#include <console/console.h>
-#include <cpu/samsung/exynos5-common/gpio.h>
#include <cpu/samsung/exynos5250/gpio.h> /* FIXME: for gpio_decode_number prototype */
#define CON_MASK(x) (0xf << ((x) << 2))
diff --git a/src/cpu/samsung/exynos5250/gpio.h b/src/cpu/samsung/exynos5250/gpio.h
index 12143849f..70e7f2d45 100644
--- a/src/cpu/samsung/exynos5250/gpio.h
+++ b/src/cpu/samsung/exynos5250/gpio.h
@@ -21,7 +21,241 @@
#ifndef EXYNOS5250_GPIO_H_
#define EXYNOS5250_GPIO_H_
-#include <cpu/samsung/exynos5-common/gpio.h>
+#include <cpu/samsung/exynos5250/cpu.h> /* FIXME: for S5PC110_GPIO_BASE */
+
+struct s5p_gpio_bank {
+ unsigned int con;
+ unsigned int dat;
+ unsigned int pull;
+ unsigned int drv;
+ unsigned int pdn_con;
+ unsigned int pdn_pull;
+ unsigned char res1[8];
+};
+
+struct s5pc100_gpio {
+ struct s5p_gpio_bank a0;
+ struct s5p_gpio_bank a1;
+ struct s5p_gpio_bank b;
+ struct s5p_gpio_bank c;
+ struct s5p_gpio_bank d;
+ struct s5p_gpio_bank e0;
+ struct s5p_gpio_bank e1;
+ struct s5p_gpio_bank f0;
+ struct s5p_gpio_bank f1;
+ struct s5p_gpio_bank f2;
+ struct s5p_gpio_bank f3;
+ struct s5p_gpio_bank g0;
+ struct s5p_gpio_bank g1;
+ struct s5p_gpio_bank g2;
+ struct s5p_gpio_bank g3;
+ struct s5p_gpio_bank i;
+ struct s5p_gpio_bank j0;
+ struct s5p_gpio_bank j1;
+ struct s5p_gpio_bank j2;
+ struct s5p_gpio_bank j3;
+ struct s5p_gpio_bank j4;
+ struct s5p_gpio_bank k0;
+ struct s5p_gpio_bank k1;
+ struct s5p_gpio_bank k2;
+ struct s5p_gpio_bank k3;
+ struct s5p_gpio_bank l0;
+ struct s5p_gpio_bank l1;
+ struct s5p_gpio_bank l2;
+ struct s5p_gpio_bank l3;
+ struct s5p_gpio_bank l4;
+ struct s5p_gpio_bank h0;
+ struct s5p_gpio_bank h1;
+ struct s5p_gpio_bank h2;
+ struct s5p_gpio_bank h3;
+};
+
+struct s5pc110_gpio {
+ struct s5p_gpio_bank a0;
+ struct s5p_gpio_bank a1;
+ struct s5p_gpio_bank b;
+ struct s5p_gpio_bank c0;
+ struct s5p_gpio_bank c1;
+ struct s5p_gpio_bank d0;
+ struct s5p_gpio_bank d1;
+ struct s5p_gpio_bank e0;
+ struct s5p_gpio_bank e1;
+ struct s5p_gpio_bank f0;
+ struct s5p_gpio_bank f1;
+ struct s5p_gpio_bank f2;
+ struct s5p_gpio_bank f3;
+ struct s5p_gpio_bank g0;
+ struct s5p_gpio_bank g1;
+ struct s5p_gpio_bank g2;
+ struct s5p_gpio_bank g3;
+ struct s5p_gpio_bank i;
+ struct s5p_gpio_bank j0;
+ struct s5p_gpio_bank j1;
+ struct s5p_gpio_bank j2;
+ struct s5p_gpio_bank j3;
+ struct s5p_gpio_bank j4;
+ struct s5p_gpio_bank mp0_1;
+ struct s5p_gpio_bank mp0_2;
+ struct s5p_gpio_bank mp0_3;
+ struct s5p_gpio_bank mp0_4;
+ struct s5p_gpio_bank mp0_5;
+ struct s5p_gpio_bank mp0_6;
+ struct s5p_gpio_bank mp0_7;
+ struct s5p_gpio_bank mp1_0;
+ struct s5p_gpio_bank mp1_1;
+ struct s5p_gpio_bank mp1_2;
+ struct s5p_gpio_bank mp1_3;
+ struct s5p_gpio_bank mp1_4;
+ struct s5p_gpio_bank mp1_5;
+ struct s5p_gpio_bank mp1_6;
+ struct s5p_gpio_bank mp1_7;
+ struct s5p_gpio_bank mp1_8;
+ struct s5p_gpio_bank mp2_0;
+ struct s5p_gpio_bank mp2_1;
+ struct s5p_gpio_bank mp2_2;
+ struct s5p_gpio_bank mp2_3;
+ struct s5p_gpio_bank mp2_4;
+ struct s5p_gpio_bank mp2_5;
+ struct s5p_gpio_bank mp2_6;
+ struct s5p_gpio_bank mp2_7;
+ struct s5p_gpio_bank mp2_8;
+ struct s5p_gpio_bank res1[48];
+ struct s5p_gpio_bank h0;
+ struct s5p_gpio_bank h1;
+ struct s5p_gpio_bank h2;
+ struct s5p_gpio_bank h3;
+};
+
+/* functions */
+void s5p_gpio_cfg_pin(struct s5p_gpio_bank *bank, int gpio, int cfg);
+void s5p_gpio_direction_output(struct s5p_gpio_bank *bank, int gpio, int en);
+void s5p_gpio_direction_input(struct s5p_gpio_bank *bank, int gpio);
+void s5p_gpio_set_value(struct s5p_gpio_bank *bank, int gpio, int en);
+unsigned int s5p_gpio_get_value(struct s5p_gpio_bank *bank, int gpio);
+void s5p_gpio_set_pull(struct s5p_gpio_bank *bank, int gpio, int mode);
+void s5p_gpio_set_drv(struct s5p_gpio_bank *bank, int gpio, int mode);
+void s5p_gpio_set_rate(struct s5p_gpio_bank *bank, int gpio, int mode);
+
+/* GPIO pins per bank */
+#define GPIO_PER_BANK 8
+
+static inline unsigned int s5p_gpio_base(int nr)
+{
+ return S5PC110_GPIO_BASE;
+}
+
+#define s5pc110_gpio_get_nr(bank, pin) \
+ ((((((unsigned int)&(((struct s5pc110_gpio *)S5PC110_GPIO_BASE)->bank))\
+ - S5PC110_GPIO_BASE) / sizeof(struct s5p_gpio_bank)) \
+ * GPIO_PER_BANK) + pin)
+
+/* Pin configurations */
+#define GPIO_INPUT 0x0
+#define GPIO_OUTPUT 0x1
+#define GPIO_IRQ 0xf
+#define GPIO_FUNC(x) (x)
+
+/* Pull mode */
+#define GPIO_PULL_NONE 0x0
+#define GPIO_PULL_DOWN 0x1
+#define GPIO_PULL_UP 0x2
+
+/* Drive Strength level */
+#define GPIO_DRV_1X 0x0
+#define GPIO_DRV_3X 0x1
+#define GPIO_DRV_2X 0x2
+#define GPIO_DRV_4X 0x3
+#define GPIO_DRV_FAST 0x0
+#define GPIO_DRV_SLOW 0x1
+
+/* GPIO pins per bank */
+#define GPIO_PER_BANK 8
+
+/* Pin configurations */
+#define EXYNOS_GPIO_INPUT 0x0
+#define EXYNOS_GPIO_OUTPUT 0x1
+#define EXYNOS_GPIO_IRQ 0xf
+#define EXYNOS_GPIO_FUNC(x) (x)
+
+/* Pull mode */
+#define EXYNOS_GPIO_PULL_NONE 0x0
+#define EXYNOS_GPIO_PULL_DOWN 0x1
+#define EXYNOS_GPIO_PULL_UP 0x3
+
+/* Drive Strength level */
+#define EXYNOS_GPIO_DRV_1X 0x0
+#define EXYNOS_GPIO_DRV_3X 0x1
+#define EXYNOS_GPIO_DRV_2X 0x2
+#define EXYNOS_GPIO_DRV_4X 0x3
+#define EXYNOS_GPIO_DRV_FAST 0x0
+#define EXYNOS_GPIO_DRV_SLOW 0x1
+
+#define EXYNOS5_GPIO_BASE0 0x11400000
+#define EXYNOS5_GPIO_BASE1 0x13400000
+#define EXYNOS5_GPIO_BASE2 0x10d10000
+#define EXYNOS5_GPIO_BASE3 0x03860000
+
+enum exynos5_gpio_port {
+ /*
+ * Ordered by base address + offset.
+ * ETC registers are special, thus not included.
+ */
+
+ /* base == EXYNOS_GPIO_BASE0 */
+ EXYNOS5_GPA0 = EXYNOS5_GPIO_BASE0 + 0x0000,
+ EXYNOS5_GPA1 = EXYNOS5_GPIO_BASE0 + 0x0020,
+ EXYNOS5_GPA2 = EXYNOS5_GPIO_BASE0 + 0x0040,
+
+ EXYNOS5_GPB0 = EXYNOS5_GPIO_BASE0 + 0x0060,
+ EXYNOS5_GPB1 = EXYNOS5_GPIO_BASE0 + 0x0080,
+ EXYNOS5_GPB2 = EXYNOS5_GPIO_BASE0 + 0x00a0,
+ EXYNOS5_GPB3 = EXYNOS5_GPIO_BASE0 + 0x00c0,
+
+ EXYNOS5_GPC0 = EXYNOS5_GPIO_BASE0 + 0x00e0,
+ EXYNOS5_GPC1 = EXYNOS5_GPIO_BASE0 + 0x0100,
+ EXYNOS5_GPC2 = EXYNOS5_GPIO_BASE0 + 0x0120,
+ EXYNOS5_GPC3 = EXYNOS5_GPIO_BASE0 + 0x0140,
+
+ EXYNOS5_GPD0 = EXYNOS5_GPIO_BASE0 + 0x0160,
+ EXYNOS5_GPD1 = EXYNOS5_GPIO_BASE0 + 0x0180,
+
+ EXYNOS5_GPY0 = EXYNOS5_GPIO_BASE0 + 0x01a0,
+ EXYNOS5_GPY1 = EXYNOS5_GPIO_BASE0 + 0x01c0,
+ EXYNOS5_GPY2 = EXYNOS5_GPIO_BASE0 + 0x01e0,
+ EXYNOS5_GPY3 = EXYNOS5_GPIO_BASE0 + 0x0200,
+ EXYNOS5_GPY4 = EXYNOS5_GPIO_BASE0 + 0x0220,
+ EXYNOS5_GPY5 = EXYNOS5_GPIO_BASE0 + 0x0240,
+ EXYNOS5_GPY6 = EXYNOS5_GPIO_BASE0 + 0x0260,
+
+ EXYNOS5_GPX0 = EXYNOS5_GPIO_BASE0 + 0x0c00,
+ EXYNOS5_GPX1 = EXYNOS5_GPIO_BASE0 + 0x0c20,
+ EXYNOS5_GPX2 = EXYNOS5_GPIO_BASE0 + 0x0c40,
+ EXYNOS5_GPX3 = EXYNOS5_GPIO_BASE0 + 0x0c60,
+
+ /* base == EXYNOS_GPIO_BASE1 */
+ EXYNOS5_GPE0 = EXYNOS5_GPIO_BASE1 + 0x0000,
+ EXYNOS5_GPE1 = EXYNOS5_GPIO_BASE1 + 0x0020,
+
+ EXYNOS5_GPF0 = EXYNOS5_GPIO_BASE1 + 0x0040,
+ EXYNOS5_GPF1 = EXYNOS5_GPIO_BASE1 + 0x0060,
+
+ EXYNOS5_GPG0 = EXYNOS5_GPIO_BASE1 + 0x0080,
+ EXYNOS5_GPG1 = EXYNOS5_GPIO_BASE1 + 0x00a0,
+ EXYNOS5_GPG2 = EXYNOS5_GPIO_BASE1 + 0x00c0,
+
+ EXYNOS5_GPH0 = EXYNOS5_GPIO_BASE1 + 0x00e0,
+ EXYNOS5_GPH1 = EXYNOS5_GPIO_BASE1 + 0x0100,
+
+ /* base == EXYNOS_GPIO_BASE2 */
+ EXYNOS5_GPV0 = EXYNOS5_GPIO_BASE2 + 0x0000,
+ EXYNOS5_GPV1 = EXYNOS5_GPIO_BASE2 + 0x0020,
+ EXYNOS5_GPV2 = EXYNOS5_GPIO_BASE2 + 0x0060,
+ EXYNOS5_GPV3 = EXYNOS5_GPIO_BASE2 + 0x0080,
+ EXYNOS5_GPV4 = EXYNOS5_GPIO_BASE2 + 0x00c0,
+
+ /* base == EXYNOS_GPIO_BASE3 */
+ EXYNOS5_GPZ = EXYNOS5_GPIO_BASE3 + 0x0000,
+};
struct exynos5_gpio_part1 {
struct s5p_gpio_bank a0;
diff --git a/src/cpu/samsung/exynos5-common/i2c.c b/src/cpu/samsung/exynos5250/i2c.c
index 30fabe165..21c939432 100644
--- a/src/cpu/samsung/exynos5-common/i2c.c
+++ b/src/cpu/samsung/exynos5250/i2c.c
@@ -30,8 +30,8 @@
#include <arch/io.h>
#include <console/console.h>
#include <device/i2c.h>
-#include "cpu/samsung/exynos5-common/clk.h"
-#include "cpu/samsung/exynos5-common/i2c.h"
+#include "cpu/samsung/exynos5250/clk.h"
+#include "cpu/samsung/exynos5250/i2c.h"
#include "cpu/samsung/exynos5250/pinmux.h"
#define I2C_WRITE 0
diff --git a/src/cpu/samsung/exynos5-common/i2c.h b/src/cpu/samsung/exynos5250/i2c.h
index 0bfee340e..0bfee340e 100644
--- a/src/cpu/samsung/exynos5-common/i2c.h
+++ b/src/cpu/samsung/exynos5250/i2c.h
diff --git a/src/cpu/samsung/exynos5250/pinmux.c b/src/cpu/samsung/exynos5250/pinmux.c
index becced24d..907ee8080 100644
--- a/src/cpu/samsung/exynos5250/pinmux.c
+++ b/src/cpu/samsung/exynos5250/pinmux.c
@@ -26,7 +26,7 @@
#include <cpu/samsung/exynos5250/gpio.h>
#include <cpu/samsung/exynos5250/cpu.h>
#include <cpu/samsung/exynos5250/pinmux.h>
-#include <cpu/samsung/exynos5-common/sromc.h>
+#include <cpu/samsung/exynos5250/sromc.h>
int exynos_pinmux_config(enum periph_id peripheral, int flags)
{
diff --git a/src/cpu/samsung/exynos5250/power.c b/src/cpu/samsung/exynos5250/power.c
index 8aba0e86b..ffba8c5f3 100644
--- a/src/cpu/samsung/exynos5250/power.c
+++ b/src/cpu/samsung/exynos5250/power.c
@@ -27,7 +27,6 @@
#include <arch/io.h>
#include <arch/hlt.h>
#include <console/console.h>
-#include <cpu/samsung/exynos5-common/power.h>
#include <cpu/samsung/exynos5250/cpu.h>
#include <cpu/samsung/exynos5250/power.h>
#include <cpu/samsung/exynos5250/sysreg.h>
diff --git a/src/cpu/samsung/exynos5250/power.h b/src/cpu/samsung/exynos5250/power.h
index 20a884eef..e82a94b7d 100644
--- a/src/cpu/samsung/exynos5250/power.h
+++ b/src/cpu/samsung/exynos5250/power.h
@@ -21,6 +21,25 @@
#ifndef __EXYNOS5_POWER_H__
#define __EXYNOS5_POWER_H__
+/*
+ * Power control
+ */
+#define S5PC100_OTHERS 0xE0108200
+#define S5PC100_RST_STAT 0xE0108300
+#define S5PC100_SLEEP_WAKEUP (1 << 3)
+#define S5PC100_WAKEUP_STAT 0xE0108304
+#define S5PC100_INFORM0 0xE0108400
+
+#define S5PC110_RST_STAT 0xE010A000
+#define S5PC110_SLEEP_WAKEUP (1 << 3)
+#define S5PC110_WAKEUP_STAT 0xE010C200
+#define S5PC110_OTHERS 0xE010E000
+#define S5PC110_USB_PHY_CON 0xE010E80C
+#define S5PC110_INFORM0 0xE010F000
+
+/* Enable HW thermal trip with PS_HOLD_CONTROL register ENABLE_HW_TRIP bit */
+void power_enable_hw_thermal_trip(void);
+
#define MIPI_PHY1_CONTROL_ENABLE (1 << 0)
#define MIPI_PHY1_CONTROL_M_RESETN (1 << 2)
diff --git a/src/cpu/samsung/exynos5-common/pwm.c b/src/cpu/samsung/exynos5250/pwm.c
index 0fc571b22..66a3b9dd3 100644
--- a/src/cpu/samsung/exynos5-common/pwm.c
+++ b/src/cpu/samsung/exynos5250/pwm.c
@@ -24,10 +24,10 @@
#include <common.h>
#include <arch/io.h>
-#include <cpu/samsung/exynos5-common/clk.h>
+#include <cpu/samsung/exynos5250/clk.h>
#include <cpu/samsung/exynos5250/cpu.h>
#include <cpu/samsung/exynos5250/periph.h>
-#include <cpu/samsung/exynos5-common/pwm.h>
+#include <cpu/samsung/exynos5250/pwm.h>
int pwm_enable(int pwm_id)
{
diff --git a/src/cpu/samsung/exynos5-common/pwm.h b/src/cpu/samsung/exynos5250/pwm.h
index d7aa76fd1..d7aa76fd1 100644
--- a/src/cpu/samsung/exynos5-common/pwm.h
+++ b/src/cpu/samsung/exynos5250/pwm.h
diff --git a/src/cpu/samsung/exynos5-common/reset.c b/src/cpu/samsung/exynos5250/reset.c
index 6cbc1d88e..6cbc1d88e 100644
--- a/src/cpu/samsung/exynos5-common/reset.c
+++ b/src/cpu/samsung/exynos5250/reset.c
diff --git a/src/cpu/samsung/exynos5-common/s5p-dp-core.h b/src/cpu/samsung/exynos5250/s5p-dp-core.h
index 4df848d0e..e7a1bd8c7 100644
--- a/src/cpu/samsung/exynos5-common/s5p-dp-core.h
+++ b/src/cpu/samsung/exynos5250/s5p-dp-core.h
@@ -251,7 +251,9 @@ void s5p_dp_wait_hw_link_training_done(struct s5p_dp_device *dp);
/* startup and init */
struct exynos5_fimd_panel;
-void fb_init(vidinfo_t *panel_info, void *lcdbase, struct exynos5_fimd_panel *pd);
+void fb_init(vidinfo_t *panel_info, void *lcdbase,
+ struct exynos5_fimd_panel *pd);
int dp_controller_init(struct s5p_dp_device *dp_device);
-int lcd_ctrl_init(vidinfo_t *panel_info, struct exynos5_fimd_panel *panel_data, void *lcdbase);
+int lcd_ctrl_init(vidinfo_t *panel_info,
+ struct exynos5_fimd_panel *panel_data, void *lcdbase);
#endif /* _S5P_DP_CORE_H */
diff --git a/src/cpu/samsung/exynos5-common/s5p-dp-reg.c b/src/cpu/samsung/exynos5250/s5p-dp-reg.c
index cce8c6d21..559019785 100644
--- a/src/cpu/samsung/exynos5-common/s5p-dp-reg.c
+++ b/src/cpu/samsung/exynos5250/s5p-dp-reg.c
@@ -12,7 +12,7 @@
#include <common.h>
#include <arch/io.h>
-#include <cpu/samsung/exynos5-common/clk.h>
+#include <cpu/samsung/exynos5250/clk.h>
#include <cpu/samsung/exynos5250/cpu.h>
#include <cpu/samsung/exynos5250/periph.h>
#include <cpu/samsung/exynos5250/s5p-dp.h>
diff --git a/src/cpu/samsung/exynos5-common/spi.c b/src/cpu/samsung/exynos5250/spi.c
index 33f4d99fd..33f4d99fd 100644
--- a/src/cpu/samsung/exynos5-common/spi.c
+++ b/src/cpu/samsung/exynos5250/spi.c
diff --git a/src/cpu/samsung/exynos5250/spi.h b/src/cpu/samsung/exynos5250/spi.h
index 20f50e58c..389291702 100644
--- a/src/cpu/samsung/exynos5250/spi.h
+++ b/src/cpu/samsung/exynos5250/spi.h
@@ -20,6 +20,9 @@
#ifndef __ASM_ARCH_EXYNOS_COMMON_SPI_H_
#define __ASM_ARCH_EXYNOS_COMMON_SPI_H_
+// This driver serves as a CBFS media source.
+#include <cbfs.h>
+
#ifndef __ASSEMBLER__
/* SPI peripheral register map; padded to 64KB */
@@ -85,5 +88,16 @@ struct exynos_spi {
#define SPI_RX_BYTE_SWAP (1 << 6)
#define SPI_RX_HWORD_SWAP (1 << 7)
+/* API */
+int exynos_spi_open(struct exynos_spi *regs);
+int exynos_spi_read(struct exynos_spi *regs, void *dest, u32 len, u32 off);
+int exynos_spi_close(struct exynos_spi *regs);
+
+/* Serve as CBFS Media */
+int initialize_exynos_spi_cbfs_media(struct cbfs_media *media,
+ void *buffer_address,
+ size_t buffer_size);
+
#endif /* __ASSEMBLER__ */
+
#endif
diff --git a/src/cpu/samsung/exynos5-common/sromc.c b/src/cpu/samsung/exynos5250/sromc.c
index 7bc93e786..7bc93e786 100644
--- a/src/cpu/samsung/exynos5-common/sromc.c
+++ b/src/cpu/samsung/exynos5250/sromc.c
diff --git a/src/cpu/samsung/exynos5-common/sromc.h b/src/cpu/samsung/exynos5250/sromc.h
index d4fdae90e..d4fdae90e 100644
--- a/src/cpu/samsung/exynos5-common/sromc.h
+++ b/src/cpu/samsung/exynos5250/sromc.h
diff --git a/src/cpu/samsung/exynos5-common/timer.c b/src/cpu/samsung/exynos5250/timer.c
index c8e419a57..e7cadc3b9 100644
--- a/src/cpu/samsung/exynos5-common/timer.c
+++ b/src/cpu/samsung/exynos5250/timer.c
@@ -27,10 +27,10 @@
#include <arch/io.h>
#include <timer.h>
#include <console/console.h>
-#include <cpu/samsung/exynos5-common/pwm.h>
-#include <cpu/samsung/exynos5-common/clk.h>
+#include <cpu/samsung/exynos5250/pwm.h>
+#include <cpu/samsung/exynos5250/clk.h>
#include <cpu/samsung/exynos5250/cpu.h>
-#include <cpu/samsung/exynos5-common/exynos5-common.h>
+#include <cpu/samsung/exynos5250/exynos5-common.h>
//#include <pwm.h>
diff --git a/src/cpu/samsung/exynos5250/uart.c b/src/cpu/samsung/exynos5250/uart.c
index 34d8e08e3..e6d9654b7 100644
--- a/src/cpu/samsung/exynos5250/uart.c
+++ b/src/cpu/samsung/exynos5250/uart.c
@@ -27,8 +27,7 @@
#include <console/console.h> /* for __console definition */
-#include <cpu/samsung/exynos5-common/exynos5-common.h>
-#include <cpu/samsung/exynos5-common/uart.h>
+#include <cpu/samsung/exynos5250/exynos5-common.h>
#include <cpu/samsung/exynos5250/uart.h>
#include <cpu/samsung/exynos5250/clk.h>
diff --git a/src/cpu/samsung/exynos5250/uart.h b/src/cpu/samsung/exynos5250/uart.h
index 1d872d705..aea4a62ca 100644
--- a/src/cpu/samsung/exynos5250/uart.h
+++ b/src/cpu/samsung/exynos5250/uart.h
@@ -32,4 +32,33 @@
#define EXYNOS5_UART3_BASE 0x12c30000
#define EXYNOS5_ISP_UART_BASE 0x13190000
+/* baudrate rest value */
+union br_rest {
+ unsigned short slot; /* udivslot */
+ unsigned char value; /* ufracval */
+};
+
+struct s5p_uart {
+ unsigned int ulcon;
+ unsigned int ucon;
+ unsigned int ufcon;
+ unsigned int umcon;
+ unsigned int utrstat;
+ unsigned int uerstat;
+ unsigned int ufstat;
+ unsigned int umstat;
+ unsigned char utxh;
+ unsigned char res1[3];
+ unsigned char urxh;
+ unsigned char res2[3];
+ unsigned int ubrdiv;
+ union br_rest rest;
+ unsigned char res3[0xffd0];
+};
+
+static inline int s5p_uart_divslot(void)
+{
+ return 0;
+}
+
#endif
diff --git a/src/cpu/samsung/exynos5250/wakeup.c b/src/cpu/samsung/exynos5250/wakeup.c
index 1e8d892bc..5a13191d5 100644
--- a/src/cpu/samsung/exynos5250/wakeup.c
+++ b/src/cpu/samsung/exynos5250/wakeup.c
@@ -19,7 +19,7 @@
#include <console/console.h>
#include <cpu/samsung/exynos5250/power.h>
-#include <cpu/samsung/exynos5-common/exynos5-common.h>
+#include <cpu/samsung/exynos5250/exynos5-common.h>
#include "wakeup.h"
diff --git a/src/cpu/samsung/exynos5-common/watchdog.h b/src/cpu/samsung/exynos5250/watchdog.h
index 5b3b651ff..5b3b651ff 100644
--- a/src/cpu/samsung/exynos5-common/watchdog.h
+++ b/src/cpu/samsung/exynos5250/watchdog.h
diff --git a/src/cpu/samsung/exynos5-common/wdt.c b/src/cpu/samsung/exynos5250/wdt.c
index dbeefec49..dbeefec49 100644
--- a/src/cpu/samsung/exynos5-common/wdt.c
+++ b/src/cpu/samsung/exynos5250/wdt.c
diff --git a/src/mainboard/google/snow/chromeos.c b/src/mainboard/google/snow/chromeos.c
index 6e46d134a..9ac3022e3 100644
--- a/src/mainboard/google/snow/chromeos.c
+++ b/src/mainboard/google/snow/chromeos.c
@@ -26,7 +26,6 @@
#include <cpu/samsung/exynos5250/cpu.h>
#include <cpu/samsung/exynos5250/gpio.h>
-#include <cpu/samsung/exynos5-common/gpio.h>
enum {
ACTIVE_LOW = 0,
diff --git a/src/mainboard/google/snow/mainboard.c b/src/mainboard/google/snow/mainboard.c
index 197735e7d..4c192fcb7 100644
--- a/src/mainboard/google/snow/mainboard.c
+++ b/src/mainboard/google/snow/mainboard.c
@@ -29,14 +29,14 @@
#include <arch/cache.h>
#include <arch/exception.h>
#include <arch/gpio.h>
-#include <cpu/samsung/exynos5-common/exynos-tmu.h>
+#include <cpu/samsung/exynos5250/exynos-tmu.h>
#include <cpu/samsung/exynos5250/clk.h>
#include <cpu/samsung/exynos5250/cpu.h>
#include <cpu/samsung/exynos5250/gpio.h>
#include <cpu/samsung/exynos5250/power.h>
-#include <cpu/samsung/exynos5-common/i2c.h>
-#include <cpu/samsung/exynos5-common/s5p-dp-core.h>
+#include <cpu/samsung/exynos5250/i2c.h>
+#include <cpu/samsung/exynos5250/s5p-dp-core.h>
#include "exynos5250.h"
diff --git a/src/mainboard/google/snow/memory.c b/src/mainboard/google/snow/memory.c
index fc5a7bde7..07079707f 100644
--- a/src/mainboard/google/snow/memory.c
+++ b/src/mainboard/google/snow/memory.c
@@ -23,7 +23,6 @@
#include <console/console.h>
#include <gpio.h>
-#include <cpu/samsung/exynos5-common/gpio.h>
#include <cpu/samsung/exynos5250/gpio.h>
#include <cpu/samsung/exynos5250/setup.h>
#include <cpu/samsung/exynos5250/dmc.h>
diff --git a/src/mainboard/google/snow/romstage.c b/src/mainboard/google/snow/romstage.c
index 3894f5a74..096db42b0 100644
--- a/src/mainboard/google/snow/romstage.c
+++ b/src/mainboard/google/snow/romstage.c
@@ -25,7 +25,7 @@
#include <arch/cache.h>
#include <arch/gpio.h>
-#include <cpu/samsung/exynos5-common/i2c.h>
+#include <cpu/samsung/exynos5250/i2c.h>
#include <cpu/samsung/exynos5250/clk.h>
#include <cpu/samsung/exynos5250/cpu.h>
#include <cpu/samsung/exynos5250/dmc.h>
diff --git a/src/mainboard/google/snow/wakeup.c b/src/mainboard/google/snow/wakeup.c
index 7a78721d0..c116c77d1 100644
--- a/src/mainboard/google/snow/wakeup.c
+++ b/src/mainboard/google/snow/wakeup.c
@@ -22,7 +22,7 @@
#include <console/console.h>
#include <cpu/samsung/exynos5250/gpio.h>
#include <cpu/samsung/exynos5250/power.h>
-#include <cpu/samsung/exynos5-common/exynos5-common.h>
+#include <cpu/samsung/exynos5250/exynos5-common.h>
#include <cpu/samsung/exynos5250/wakeup.h>